3D Memory Through Array Contacts Without Barrier Structures
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Solution Overview
Problem
The existing fabrication processes for 3D memory devices face challenges in forming through array contacts (TACs) enclosed by barrier structures, which increase area usage in the core array region, impact word line resistance, and become more complex for next-generation devices with higher levels, limiting memory cell density and process margin.
Innovation Solution
The formation of 3D memory devices without barrier structures for TACs, allowing for reduced area usage and simplified fabrication by integrating TACs with other structures like peripheral contacts and dummy channel structures, thereby increasing memory cell density and process extendibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If barrier structures are used to enclose TACs, then TAC formation is enabled, but area usage increases and device complexity increases
Solution Approach 1:
The patent extracts and removes the barrier structure from the TAC formation process. Instead of enclosing TACs with barrier structures, the invention forms TACs directly through the dielectric stack using a simplified process that etches openings and fills them with conductor material, eliminating the need for barrier structures entirely and reducing area usage in the core array region
Solution Approach 2:
The patent transitions from a planar 2D approach with barrier structures enclosing TACs to a vertical 3D approach where TACs extend through the dielectric stack in the vertical dimension. This dimensional change allows TACs to be formed without lateral barrier enclosures, reducing the footprint area while maintaining functionality
2Ease of manufacture
If barrier structures are used to enclose TACs, then TAC formation is enabled, but fabrication process complexity increases
Solution Approach 1:
The patent extracts and removes the barrier structure formation steps from the fabrication process. The simplified method directly forms TACs by etching openings through the dielectric stack and filling them with conductor material, eliminating multiple process steps related to barrier structure deposition, patterning, and etching that would increase fabrication complexity
Solution Approach 2:
The patent merges the TAC formation process with other fabrication steps. The same opening etching and conductor filling processes used for forming TACs are also used for forming peripheral contacts and other structures, consolidating multiple operations into unified process steps that reduce overall fabrication complexity
3Ease of manufacture
If barrier structures are used to enclose TACs, then TAC formation is enabled, but memory cell density decreases
Solution Approach 1:
By removing barrier structures from the TAC design, the patent frees up lateral space in the core array region. This extracted space can be reallocated to accommodate additional memory cells or reduce the pitch between cells, directly increasing memory cell density while maintaining TAC functionality
Solution Approach 2:
The patent moves TAC functionality into the vertical dimension by having TACs extend through the dielectric stack height rather than being enclosed in the lateral plane. This vertical integration allows lateral space to be used more efficiently for memory cell arrays, increasing density without compromising TAC formation capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory cell density, reduces process costs, and provides more process margin by eliminating the need for barrier structures, making it suitable for current and future generations of 3D memory devices.
Implementation Method 1
A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening
Implementation Method 2
A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening
Data Source
AI summary
In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.