3D Memory Slit Structure With Tapered Width for Leakage Control
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, traditional planar memory fabrication techniques become challenging and costly, and 3D memory architecture is needed to enhance memory density, but controlling the gate line slit structure in 3D memory devices is difficult, leading to issues like metal residue and word line current leakage.
Innovation Solution
A 3D memory device with a stack structure comprising interleaved conductive and dielectric layers, including a staircase structure and slit structure, where the slit structure is formed by creating openings from both sides of the stack, allowing for improved etch operations and reduced profile abnormalities, and word lines are formed by replacing sacrificial layers, enhancing the control over the gate line slit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar memory fabrication techniques are used, then manufacturing process is simple, but memory density is limited and feature sizes approach lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory architecture to three-dimensional (3D) memory architecture by stacking multiple memory layers vertically. This dimensional change enables significantly higher memory density without requiring further reduction of feature sizes, as memory cells are arranged in multiple levels along the vertical axis rather than only in a single plane.
Solution Approach 2:
The 3D memory device is divided into multiple stacked layers, each containing memory cells, word lines, and bit lines. This segmentation allows independent fabrication and optimization of each layer, enabling complex 3D structures to be built through repeated modular stacking processes, thereby managing fabrication complexity while achieving high density.
2Quantity of substance
If 3D memory architecture is implemented, then memory density is enhanced, but controlling gate line slit structure becomes difficult
Solution Approach 1:
The patent introduces a sacrificial layer structure that is formed in advance before the actual word line formation. This preliminary sacrificial structure serves as a template and support during the etching process, enabling precise control of the gate line slit structure. The sacrificial layer is removed after serving its guiding function, leaving behind the precisely formed word lines with controlled slits.
Solution Approach 2:
The sacrificial layer acts as an intermediary element that facilitates the formation of the gate line slit structure. It provides a temporary physical structure that guides the etching process and ensures precise word line formation, then is removed after completing its mediating function. This intermediary approach solves the difficulty of directly controlling complex 3D slit structures.
3Reliability
If gate line slit structure control is poor, then metal residue and word line current leakage occur
Solution Approach 1:
The sacrificial layer is formed in advance to define the precise geometry of the future word line slits. This preliminary structure ensures that the etching process follows the intended path accurately, preventing metal residue by completely removing sacrificial material and ensuring clean slit formation. The pre-defined structure eliminates variability in slit dimensions that could lead to reliability issues.
Solution Approach 2:
The sacrificial layer structure provides built-in feedback during the etching process by maintaining its physical form as a reference. The etch process is monitored and controlled relative to the sacrificial layer boundaries, ensuring that word lines are formed with precise dimensions and proper spacing. This feedback mechanism prevents over-etching or under-etching that could cause metal residue or current leakage.
4Productivity
If process window for forming slit structure is narrow, then fabrication yield decreases
Solution Approach 1:
The patent employs the sacrificial layer with specific material properties and dimensions that are optimized to provide a robust process window. By changing parameters such as sacrificial layer thickness, material composition, and formation conditions, the process becomes more tolerant to variations in etching conditions. This parameter optimization expands the acceptable process range, thereby increasing fabrication yield while maintaining slit structure precision.
Data Source
AI summary
A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.