3D Memory With Overlying TFT Control Circuit Integration
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in integrating efficient thin film transistor control circuits with three-dimensional memory devices, particularly in manufacturing processes that require precise integration of insulating and conductive layers to form functional memory elements and peripheral circuits.
Innovation Solution
The semiconductor structure includes a three-dimensional memory device with alternating stacks of insulating and conductive layers, memory openings filled with vertical semiconductor channels and memory elements, and thin film transistors formed between the memory device and bonding pads, along with a logic die bonded to the memory die, enabling a comprehensive control circuit for the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thin film transistors are integrated within the memory device structure, then operational control is enhanced, but device complexity increases
Solution Approach 1:
The thin film transistor control circuit is nested within the three-dimensional memory device structure, with the TFT layer integrated between the memory stack and bonding pads. This nesting approach allows the control circuit to be embedded within the existing memory architecture rather than added as a separate component, enhancing operational control while managing device complexity through spatial integration.
Solution Approach 2:
The patent utilizes vertical stacking to integrate the thin film transistor control circuit in the z-dimension, above the memory openings and alternating layers. This dimensional approach allows the control circuit to be added without increasing the lateral footprint of the memory device, resolving the contradiction by adding functionality in a different spatial dimension rather than expanding the existing structure.
2Reliability
If alternating stacks of insulating and conductive layers are formed with precise integration, then memory element functionality is improved, but manufacturing precision requirements increase
Solution Approach 1:
The insulating and conductive layers are formed in a predetermined alternating sequence during the manufacturing process, with each layer prepared and positioned before the next is added. This preliminary action approach ensures that the precise integration required for memory element functionality is built into the fabrication process itself, allowing standard manufacturing techniques to achieve the required precision without excessive complexity.
Data Source
AI summary
A semiconductor structure includes a memory die and a logic die. The memory die includes a three-dimensional memory device that contains an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the two-dimensional array of memory openings, where each of the memory opening fill structures includes a respective vertical semiconductor channel, a respective drain region, and a vertical stack of memory elements located at levels of the electrically conductive layers, memory-side bonding pads, and a first peripheral circuit including first thin film transistors located between the three-dimensional memory device and the memory-side bonding pads. The logic die includes a logic-side substrate, logic-side bonding pads bonded to the memory-side bonding pads, and a second peripheral circuit located between the logic-side substrate and the logic-side bonding pads.