3D Vertical Memory Stack With Thermal-Protective Insulating Layers
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity while maintaining integration and reliability.
Innovation Solution
A semiconductor device with a lower structure featuring a semiconductor substrate, circuit elements, and a circuit interconnection structure with multiple connection patterns, and an upper structure with a stack of interlayer insulating layers and gate electrodes, along with a vertical memory structure. The lower insulating structure includes a first insulating layer, a capping layer with a different material, and a second insulating layer, which enhances integration and protects against thermal damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple connection patterns and insulating layers vertically. This enables increased storage capacity by utilizing the vertical dimension, where multiple connection patterns (first, second, third connection patterns) are arranged at different heights and connected through contact plugs, effectively multiplying the storage capacity without proportionally increasing planar footprint or overall device complexity.
2Productivity
If multiple connection patterns are stacked vertically to increase integration, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the connection structure into multiple discrete connection patterns (first connection pattern, second connection pattern, third connection pattern) separated by insulating layers. Each connection pattern can be independently formed and positioned, allowing for modular manufacturing processes. Contact plugs are used to establish electrical connections between these segmented layers, enabling high integration while maintaining manageable manufacturing precision through staged fabrication processes.
Solution Approach 2:
The patent introduces contact plugs as intermediary elements that facilitate electrical connections between the vertically stacked connection patterns. These contact plugs act as mediators that bridge the gap between different connection patterns separated by insulating layers, enabling complex multi-layer interconnections while simplifying the manufacturing process by providing standardized connection points between layers.
3Reliability
If a multi-layer insulating structure is used to protect circuit elements, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent employs a composite insulating structure consisting of multiple insulating layers (first insulating layer, second insulating layer, third insulating layer) with different materials and properties. Each layer provides specific protective functions, such as electrical isolation, mechanical support, or thermal management. This composite approach enhances reliability by addressing multiple failure modes simultaneously while distributing the functional requirements across different layers, thereby managing overall device complexity through functional specialization.
Data Source
AI summary
A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a lower structure including a semiconductor substrate, a circuit element on the semiconductor substrate, a circuit interconnection structure on the semiconductor substrate, the circuit interconnection structure including a plurality of connection patterns on different levels and electrically connected to the circuit element, and a lower insulating structure covering the circuit element and the circuit interconnection structure; and an upper structure including an upper substrate in contact with an upper surface of the lower insulating structure, a stack structure on the upper substrate, the stack structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, and a vertical memory structure penetrating through the stack structure in the vertical direction.