3D Memory Conductive Layers via Local Thickness Control
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming vertically stacked NAND strings with uniform and reliable electrically conductive layers, particularly in achieving the necessary thickness variations and stepped surfaces for optimal performance.
Innovation Solution
A method involving the formation of an alternating stack of insulating and sacrificial material layers over a substrate, followed by patterning to create stepped surfaces and dielectric pillar structures, and subsequent replacement with electrically conductive layers, ensuring lateral extent reduction with vertical distance and specific thickness variations in the staircase region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If uniform electrically conductive layers are formed in conventional three-dimensional memory devices, then manufacturing simplicity is maintained, but the ability to achieve necessary thickness variations and stepped surfaces for optimal performance is lost
Solution Approach 1:
The patent applies local quality by creating non-uniform electrically conductive layers with different thicknesses in different regions. Specifically, the electrically conductive layers have a first thickness in a first area, a second thickness in a distal segment of a second area, and a third thickness in a proximal segment of the second area, where the second thickness is greater than the first thickness. This local variation in thickness enables optimized electrical performance in different regions of the memory device while maintaining the overall staircase structure.
2Quantity of substance
If vertically stacked NAND strings are formed with high density, then memory capacity increases, but the reliability of electrically conductive layers and consistency of formation processes deteriorate
Solution Approach 1:
The patent segments the electrically conductive layers into multiple distinct thickness regions (first area with first thickness, distal segment with second thickness, proximal segment with third thickness). This segmentation allows each region to be independently optimized for its specific function while maintaining overall device reliability. The alternating stack structure is also segmented into insulating layers and sacrificial material layers that are selectively removed and replaced, enabling precise control over the final conductive layer configuration.
Solution Approach 2:
The patent employs preliminary action by forming sacrificial material layers in advance with specific lateral extents that decrease with vertical distance from the substrate. These sacrificial layers are then selectively removed and replaced with electrically conductive material. This preliminary structuring enables precise thickness control and stepped surface formation before the final conductive layers are deposited, ensuring consistent formation processes even in high-density vertically stacked configurations.
3Reliability
If stepped surfaces with decreasing lateral extent are created in the staircase region, then optimal electrical performance is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent utilizes another dimension by creating stepped surfaces where the lateral extent of sacrificial material layers decreases with vertical distance from the substrate. This three-dimensional staircase structure is formed by depositing alternating insulating and sacrificial layers with progressively reduced lateral dimensions at each level. The vertical stacking combined with lateral reduction creates the stepped configuration that enables optimal electrical performance while the systematic layer-by-layer approach maintains manufacturing feasibility.
Data Source
AI summary
Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.