3D Memory Device Thinned Insulating Layers
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming vertical NAND strings with optimal insulating and conductive layer thicknesses, leading to suboptimal performance and reliability.
Innovation Solution
A method involving the formation of an alternating stack of insulating and sacrificial material layers over a substrate, followed by the creation of memory openings and fill structures with specific dielectric and charge storage layers, and subsequent etching processes to form backside recesses and conductive layers, ensuring word lines are thicker than insulating layers for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If insulating layers are made thinner to increase storage density, then device capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the thickness of insulating layers and sacrificial material layers to optimize both storage density and manufacturability. Different layer thicknesses are used at different stages of the process, with thinner insulating layers (e.g., 5-20 nm) used in final high-density configurations while maintaining thicker sacrificial layers during manufacturing for better process control.
Solution Approach 2:
The patent segments the memory structure into multiple alternating layers of insulating material and sacrificial material, each with optimized thickness. This segmentation allows independent optimization of each layer's thickness - the insulating layers can be made thin for high density while sacrificial layers remain thicker to provide manufacturing tolerance and structural support during fabrication.
2Reliability
If word lines are made thicker than insulating layers to improve electrical performance, then conductivity increases, but device complexity increases
Solution Approach 1:
The patent employs asymmetry by making word lines deliberately thicker than the insulating layers. This asymmetric design provides superior electrical conductivity and reliability for the word lines (which carry current) while keeping insulating layers thin to maintain high storage density. The asymmetric thickness relationship (word line thickness > insulating layer thickness) is maintained throughout the stacked structure.
Solution Approach 2:
The patent transitions to three-dimensional vertical stacking where word lines and insulating layers are arranged in alternating vertical tiers. This dimensional change from planar to vertical architecture allows thick word lines to coexist with thin insulating layers without increasing lateral footprint, thereby improving electrical performance while maintaining compact device geometry.
3Manufacturing precision
If multiple etching processes are used to form backside recesses with precise dimensions, then manufacturing precision improves, but productivity decreases
Solution Approach 1:
The patent performs preliminary actions by forming the alternating stack of insulating and sacrificial material layers with precise thickness ratios before the etching step. The sacrificial layers are deposited with controlled thickness that pre-determines the final backside recess dimensions after selective removal. This preliminary precision control reduces the need for multiple iterative etching adjustments, improving both precision and productivity.
Solution Approach 2:
The patent uses sacrificial material layers as intermediaries to achieve precise backside recess formation. These sacrificial layers are deposited with controlled thickness and then selectively removed through etching, using the insulating layers as etch stops. This intermediary approach allows precise dimension control without requiring complex multi-step etching processes, as the sacrificial layer thickness directly defines the recess geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the structural integrity and performance of three-dimensional memory devices by ensuring precise control over layer thicknesses, leading to improved reliability and efficiency in data storage.
Implementation Method 1
expanding the backside recesses by isotropically etching surface portions of the insulating layers employing a remote-plasma-assisted dry etch process or a chemical dry etch process
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of word lines and at least one insulating layers or air gaps located over a substrate, a memory opening fill structure extending through the alternating stack. The memory opening fill structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The word lines are thicker than the insulating layers or air gaps.