3D Memory Source Contact Structure for Backside Thinning Control
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Solution Overview
Problem
The production of 3D NAND memory devices faces challenges in thickness uniformity control during substrate thinning and achieving deep, high concentration doping, which limits yield and complexity in backside processes due to the sidewall selective epitaxial growth (SEG) structure.
Innovation Solution
A stop layer is formed to control the backside thinning process and channel hole etching, allowing for complete substrate removal and using deposited polysilicon layers as sidewall SEG, which can be easily doped to achieve desired doping concentrations, reducing fabrication complexity and increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If substrate thinning is performed to achieve desired thickness, then thickness uniformity is improved, but gouging variations and parasitic capacitance occur
Solution Approach 1:
The patent removes the substrate entirely through backside etching instead of thinning it. The stop layer is etched away completely, allowing the substrate to be fully removed. This extraction approach eliminates the harmful effects of substrate thinning (gouging variations and parasitic capacitance) while achieving the desired thin structure for the memory device.
Solution Approach 2:
The substrate is treated as a temporary, disposable structure that is completely removed after serving its purpose during fabrication. By using the substrate only as a temporary support during the formation process and then removing it entirely, the patent avoids the long-term harmful effects of substrate presence (parasitic capacitance) while achieving precise thickness control during the fabrication process.
2Quantity of substance
If sidewall selective epitaxial growth (SEG) structure is used, then doping concentration can be achieved, but fabrication complexity increases
Solution Approach 1:
The patent changes the material parameter from requiring high-concentration doping through complex SEG processes to using inherently high-concentration polysilicon material. By depositing polysilicon directly as the sidewall structure, the patent achieves the desired doping concentration without the complex multi-step SEG fabrication process, thereby reducing fabrication complexity while maintaining the required electrical properties.
Solution Approach 2:
The patent replaces the complex SEG process with a simpler polysilicon deposition approach. Instead of using the elaborate sidewall selective epitaxial growth process, the patent uses direct polysilicon deposition which is simpler, faster, and achieves the same or better doping concentrations, thereby reducing fabrication complexity.
3Reliability
If channel structures extend through polysilicon layer, then electrical contact is achieved, but thickness control becomes difficult
Solution Approach 1:
The patent introduces a stop layer as an intermediary structure between the substrate and the polysilicon layer. This stop layer serves as a precise thickness reference and etch stop point, allowing channel structures to extend through the polysilicon layer with controlled depth. The stop layer mediates between the need for electrical contact and the need for precise thickness control by providing a well-defined termination point for etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves thickness uniformity, reduces fabrication complexity, and increases the production yield of 3D NAND memory devices by enabling easier doping and avoiding issues like gouging variations and parasitic capacitance.
Implementation Method 1
A stop layer is formed to control the backside thinning process and channel hole etching
Implementation Method 2
using deposited polysilicon layers as sidewall SEG, which can be easily doped to achieve desired doping concentrations
Data Source
AI summary
A semiconductor device includes a first dielectric layer, a source layer at a first side of the first dielectric layer and in contact with the first dielectric layer, a second dielectric layer at a second side opposite to the first side of the first dielectric layer and in contact with the first dielectric layer, a source contact structure extending vertically through the second dielectric layer and the first dielectric layer, and extending into the source layer and without penetrating through the source layer, a stack including interleaved stack conductive layers and stack third dielectric layers, the source layer being located between the first dielectric layer and the stack in a vertical direction, a channel structure extending vertically through the stack and the source layer, and an insulating structure extending vertically through the stack into the source layer. In the vertical direction, a length of the channel structure in the source layer is greater than a length of the insulating structure in the source layer. A sidewall of the insulating structure includes a plurality of protruding structures protruding toward the conductive layers.