3D Nonvolatile Memory Threshold Control for Adjacent Cell Interference
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Solution Overview
Problem
As semiconductor memory devices downscale, interference between adjacent memory cells affects data reliability, particularly for multi-bit storage, due to fluctuations in memory cell transistor thresholds caused by adjacent cell information, which also impacts data retention characteristics.
Innovation Solution
A nonvolatile semiconductor memory device with a control unit that sets memory cell transistors to specific thresholds for multi-bit information storage by programming charges in storage regions, including an erase threshold and additional thresholds for each bit value, and adjusts adjacent cell thresholds to minimize interference, using a three-dimensionally stacked structure with charge storage films and insulating films to enhance data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are downscaled to increase storage capacity, then storage density is improved, but interference between adjacent cells increases causing threshold fluctuations and reduced data reliability
Solution Approach 1:
The memory array is divided into multiple blocks, and within each block, memory cells are organized into distinct stacks with separate charge storage films. This segmentation isolates adjacent cells physically and electrically, reducing interference while maintaining high storage density through vertical stacking.
Solution Approach 2:
Insulating films are introduced as intermediary layers between adjacent memory cells and between the charge storage film and other structures. These intermediary insulating films act as barriers that prevent electrical interference and charge leakage, thereby maintaining threshold stability despite cell downsizing.
2Productivity
If multi-bit information is stored in one memory cell to increase capacity, then storage efficiency is improved, but threshold fluctuations due to adjacent cell information increase causing reduced data retention
Solution Approach 1:
The memory cell structure is segmented into multiple independent charge storage films, each capable of storing one bit of information. This segmentation enables multi-bit storage per cell while isolating the charge storage regions to minimize mutual interference, thereby maintaining data retention characteristics.
Solution Approach 2:
Different charge storage films within the same memory cell are configured with locally optimized properties, including varying thicknesses and material compositions tailored to specific bit positions. This local quality optimization reduces threshold fluctuations caused by adjacent bit information while preserving multi-bit storage capability.
3Area of stationary object
If three-dimensional stacked structures are used to downscale memory cells, then area efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
Multiple charge storage films and insulating layers are nested vertically within compact three-dimensional stacked structures. This nesting approach achieves high area efficiency by utilizing vertical space while maintaining a relatively compact footprint that simplifies integration into existing semiconductor manufacturing processes.
Solution Approach 2:
The memory structure transitions from two-dimensional planar布局 to three-dimensional vertical stacking, adding the vertical dimension to increase storage capacity per unit area. This dimensional change improves area efficiency while the standardized stacking approach helps manage manufacturing complexity through repeatable process modules.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film and a memory cell transistor. The transistor is provided for each of storage regions configured to store charge in the film. The control unit sets the transistors to an erase threshold by setting erase information in the regions; subsequently sets the transistors to thresholds corresponding to information having n values by programming the information having the n values to at least one of the regions in which the erase information is set; and controls information of at least one storage region before being programmed adjacent to the regions programmed with the information to have a value providing a threshold of the transistor nearer than the erase threshold to the thresholds corresponding to the information having the n values in the state of the transistors provided in the regions being set to the thresholds corresponding to the information having the n values.