3D Memory Device with Locally Modulated Threshold Voltages
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving locally modulated threshold voltages at drain select levels, which are essential for efficient memory operation, due to limitations in manufacturing methods and device design.
Innovation Solution
A three-dimensional memory device is designed with an alternating stack of insulating and electrically conductive layers, including word lines and drain select gate electrodes, where memory stack structures have vertically oriented semiconductor channels and charge storage layers with varying thicknesses to modulate threshold voltages, and a method involving the formation of memory openings with laterally bulging regions to enhance charge storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If uniform charge storage layers are used in all memory stack structures, then manufacturing process is simple, but threshold voltage modulation at drain select levels is not achieved
Solution Approach 1:
The patent implements local quality by creating charge storage layers with different thicknesses at specific locations. The first charge storage layer has a first thickness at the first drain select gate electrode level, while the second charge storage layer has a second thickness at the second drain select gate electrode level. This local variation in thickness enables precise threshold voltage modulation at different drain select levels without requiring complete redesign of the entire memory structure.
2Quantity of substance
If laterally bulging regions are formed in all memory openings, then charge storage capacity is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by forming laterally bulging regions selectively in specific memory openings rather than uniformly in all openings. The first set of memory openings has laterally bulging regions that extend laterally beyond the vertical sidewalls, while the second set of memory openings does not have such bulging regions. This segmented approach enhances charge storage capacity in critical areas while maintaining manufacturing feasibility.
3Ease of operation
If varying thickness charge storage layers are implemented, then threshold voltage control is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by forming the alternating stack of insulating layers and charge storage layers with predetermined thickness variations before subsequent processing steps. The first charge storage layer is formed with a first thickness and the second charge storage layer with a second thickness during the initial layer formation process. This preliminary establishment of thickness variations simplifies later threshold voltage control operations while maintaining achievable manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables precise control of threshold voltages across drain select transistors, improving memory device performance by allowing for selective activation and deactivation of memory strings, thereby enhancing data storage efficiency and density.
Implementation Method 1
a memory film including a tunneling dielectric and a charge storage layer
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.