3D Semiconductor Memory Stack with Vertical Channels and Through Contacts
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Solution Overview
Problem
Current two-dimensional semiconductor devices face limitations in integration and cost due to the need for expensive processing equipment to achieve fine pattern formation, which hinders their ability to store large amounts of data effectively.
Innovation Solution
A three-dimensional semiconductor memory device is developed with a vertical channel structure, featuring a stack structure with interlayer dielectric layers and gate electrodes, cell contact plugs, selection mold structures, and spacer dielectric layers, which enhances integration and reliability while reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar semiconductor devices are highly integrated to store large amounts of data, then data storage capacity is improved, but manufacturing cost increases due to expensive processing equipment required for fine pattern formation
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertical channel structures. The vertical channels extend through multiple stacked layers (first dielectric layer, second dielectric layer, third dielectric layer) with gate electrodes positioned at different heights, enabling data storage in the vertical dimension rather than only in the planar dimension. This dimensional transition increases storage capacity without requiring proportionally finer lateral patterning, thereby reducing dependence on expensive fine-patterning equipment.
2Manufacturing precision
If fine pattern formation is achieved in two-dimensional semiconductor devices, then integration density is improved, but manufacturing complexity increases due to expensive processing equipment
Solution Approach 1:
The invention forms vertical channels that extend in the vertical direction through stacked dielectric layers, shifting the complexity from lateral fine patterning to vertical stacking. The vertical channel structures are formed using standard photolithography and etching processes without requiring extreme ultraviolet (EUV) or other advanced fine-patterning tools. The stacking of dielectric layers and gate electrodes creates the three-dimensional structure through sequential layer deposition and patterning, which uses conventional manufacturing equipment.
Solution Approach 2:
The device is segmented into multiple stacked layers (first dielectric layer with first gate electrode, second dielectric layer with second gate electrode, third dielectric layer with third gate electrode) that can be formed and processed separately in sequential steps. Each layer can be patterned and assembled independently using standard processes, avoiding the need to form all features in a single complex fine-patterning step. This segmentation of the structure into manageable stacked components reduces processing complexity.
Data Source
AI summary
A three-dimensional semiconductor memory device comprises a first substrate including a cell array region and a contact region, a stack structure including interlayer dielectric layers and gate electrodes on the first substrate, a second dielectric layer on the stack structure, a cell contact plug that extends through the second dielectric layer and the contact region, a selection mold structure on the stack structure and the second dielectric layer, a third dielectric layer on the selection mold structure, and a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug. The dummy through contact has a second width. The capping through contact has a first width. The second width is different from the first width.