3D Semiconductor Memory Stack With Through-Plug Backside Interconnect
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost and complexity of equipment needed to form fine patterns, making it difficult to increase storage capacity while maintaining manufacturing efficiency.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a peripheral circuit structure, a cell array structure, and a backside structure, featuring through plugs and connection plugs that facilitate electrical connections between these components, allowing for increased storage capacity without damaging peripheral transistors during manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices are integrated to increase storage capacity, then storage density is improved, but manufacturing cost and complexity increase due to expensive fine pattern equipment
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, enabling increased storage capacity without requiring finer lateral patterning. This dimensional change allows achieving higher integration density while avoiding the need for increasingly complex and expensive fine pattern processing equipment.
Solution Approach 2:
The memory device is divided into multiple independent memory cell layers stacked vertically. Each layer can be fabricated using similar processes, and the modular structure allows for systematic scaling of storage capacity by adding more layers rather than continuously reducing feature sizes in a single plane.
2Ease of manufacture
If peripheral circuit structure and cell array structure are manufactured separately and then bonded, then ease of manufacture is improved, but device complexity increases due to additional bonding processes
Solution Approach 1:
The memory device is segmented into a peripheral circuit structure and a cell array structure that are manufactured separately on different substrates. The peripheral circuit structure contains control logic and interface circuits, while the cell array structure contains the stacked memory cells. These separate structures are then bonded together through bonding pads, allowing each to be optimized independently while simplifying the overall manufacturing process.
Solution Approach 2:
Bonding pads are introduced as intermediary elements that facilitate the connection between the peripheral circuit structure and the cell array structure. These bonding pads enable electrical and mechanical coupling between the separately manufactured structures, allowing modular assembly while maintaining electrical connectivity.
3Reliability
If through plugs extend through the stack structure to connect backside structure and middle circuit structure, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
Through plugs are formed extending through the entire stack structure before the final bonding step. This preliminary formation of through plugs ensures that electrical pathways are established in advance, allowing for subsequent bonding operations to focus primarily on alignment and connection rather than simultaneous formation of multiple complex features.
Solution Approach 2:
The through plugs serve as intermediary conductive elements that bridge the backside structure and the middle circuit structure. By providing dedicated conductive pathways through the insulating stack structure, they simplify the bonding process and reduce the precision requirements for aligning multiple circuit features during assembly.
Data Source
AI summary
Disclosed is a semiconductor device comprising a peripheral circuit structure on a first substrate, a cell array structure on the peripheral circuit structure, and a backside structure on the cell array structure. The cell array structure includes a stack structure including gate electrodes and interlayer dielectric layers that are alternately stacked, through plugs that extend in a first direction through the stack structure and each including a first surface adjacent to the backside structure and a second surface opposite to the first surface, a middle circuit structure between the stack structure and the peripheral circuit structure and connected to the peripheral circuit structure, and a connection plug connected to the middle circuit structure and the backside structure. The through plugs include a first through plug connected through the first surface to the backside structure, and a second through plug connected through the second surface to the middle circuit structure.