3D Semiconductor Memory Stack with Through Structures for Higher Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional two-dimensional semiconductor devices face limitations in integration and cost due to the need for expensive equipment for fine pattern formation, while three-dimensional semiconductor memory devices aim to increase storage capacity and reliability.
Innovation Solution
A three-dimensional semiconductor memory device with a vertical channel structure, including a stack structure of interlayer dielectric layers and gate electrodes, a dielectric layer, and a mold structure with through structures, which enhances integration and electrical properties by reducing the number of capacitors in the peripheral circuit and providing a reduced electrical connection path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited due to area constraints and expensive equipment requirements for fine patterns
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory cells. The stack structure includes multiple memory cell strings arranged in the vertical direction, with gate electrodes (word lines) and bit lines extending vertically through the stack. This dimensional change enables significantly higher integration density without requiring proportionally more expensive fine-patterning equipment, as the vertical stacking leverages existing planar fabrication processes while adding the third dimension for increased capacity.
2Productivity
If three-dimensional vertically stacked memory cells are implemented, then integration is increased, but device complexity increases due to additional structures like stack structures, separation dams, and through structures
Solution Approach 1:
The patent divides the three-dimensional memory structure into distinct functional segments: stack structures containing memory cell strings, peripheral circuit structures for control logic, separation dam structures for isolation, and through structures for inter-layer connectivity. Each segment performs a specific function and can be independently optimized or manufactured. The stack structures are separated into multiple blocks, and the separation dams create distinct regions for different circuit functions, enabling modular design that manages complexity through functional decomposition.
Solution Approach 2:
The patent introduces intermediary structures to manage the complexity of three-dimensional integration. Separation dam structures act as intermediaries between adjacent memory blocks, providing electrical isolation and mechanical support. Through structures serve as intermediaries for signal routing between different vertical levels and between memory arrays and peripheral circuits. These intermediary elements simplify the overall system by creating clear boundaries and standardized interfaces between complex subsystems.
3Reliability
If peripheral circuit structures are integrated with memory arrays in three-dimensional configuration, then electrical connection path is reduced, but manufacturing precision requirements increase for aligning multiple stacked layers
Solution Approach 1:
The patent implements a nested hierarchical structure where memory cell strings are nested within stack structures, which are in turn nested within larger memory blocks separated by separation dams. Through structures are nested to penetrate multiple stacked layers, creating direct electrical pathways from upper memory cells to lower peripheral circuits. This nested arrangement reduces the electrical connection path length by allowing vertical signals to traverse directly through stacked layers rather than routing laterally through intermediate connection layers, while the self-aligned nature of vertical stacking reduces precision requirements compared to lateral alignment.
Data Source
AI summary
Disclosed are three-dimensional semiconductor memory devices and electronic systems. The three-dimensional semiconductor memory device includes a first substrate that includes a cell array region and a contact region, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure wherein the cell array structure includes interlayer dielectric layers and gate electrodes that are alternately stacked, a dielectric layer on the stack structure, and a second substrate on the stack structure, a mold structure that penetrates the stack structure and includes a dielectric material, and a first through structure and a second through structure that penetrate the mold structure and are spaced apart from each other.