3D Memory Through-Via Structure for Alignment and Capacitance Control
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Solution Overview
Problem
The integration density of two-dimensional semiconductor devices is limited by the need for expensive equipment to form fine patterns, and three-dimensional semiconductor memory devices are needed to overcome these limitations while ensuring reliability and improved integration.
Innovation Solution
A 3D semiconductor memory device with a peripheral circuit structure, intermediate insulating layer, and cell array structure, featuring through-vias with varying widths and insulating patterns to connect electrode layers to the peripheral circuit, reducing misalignment and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-vias with uniform width are used to connect electrode layers to peripheral circuit, then manufacturing process is simple, but misalignment occurs between different layers reducing reliability
Solution Approach 1:
The through-via is divided into multiple segments with different widths corresponding to different layers. The first via portion has a first width matching the planarization insulating layer, while the second via portion has a second width matching the intermediate insulating layer, allowing each segment to align properly with its respective layer without requiring complex alignment processes.
Solution Approach 2:
Different portions of the through-via are given different local properties (widths) to match the requirements of different layers. The first via portion is wider to match the planarization insulating layer opening, while the second via portion is narrower to match the intermediate insulating layer opening, optimizing alignment and connection reliability for each local region.
2Productivity
If conventional through-via structures are used, then manufacturing process is straightforward, but parasitic capacitance increases affecting device performance
Solution Approach 1:
The via insulating pattern is segmented into multiple portions (first, second, and third insulating portions) that are strategically positioned around different segments of the through-via. This segmentation allows insulation to be applied where needed to reduce parasitic capacitance while maintaining manufacturing simplicity.
Solution Approach 2:
The via insulating pattern acts as an intermediary element between the through-via and surrounding structures. By positioning insulating portions at specific locations (such as between the first via portion and planarization insulating layer, and between the second via portion and intermediate insulating layer), it reduces parasitic capacitance without complicating the overall manufacturing process.
3Manufacturing precision
If fine patterns are formed in 2D semiconductor devices to increase integration density, then integration density improves, but expensive equipment is required
Solution Approach 1:
The patent transitions from two-dimensional planar interconnection to three-dimensional vertical interconnection through the use of through-vias that penetrate multiple layers. This dimensional change allows integration density to increase without requiring finer lateral patterning, thereby avoiding the need for expensive fine-patterning equipment while achieving higher integration.
Data Source
AI summary
A 3D semiconductor memory device includes a peripheral circuit structure, an intermediate insulating layer and a cell array structure. The cell array structure includes a first substrate including a cell array region and a connection region; a stack structure comprising electrode layers and electrode interlayer insulating layers alternately stacked on the first substrate; a planarization insulating layer covering an end portion of the stack structure on the connection region; and a first through-via penetrating the planarization insulating layer, the first substrate and the intermediate insulating layer. The first through-via connects one of the electrode layers to the peripheral circuit structure. The first through-via includes a first and second via portion integrally connected to each other. The first via portion penetrates the planarization insulating layer and has a first width. The second via portion penetrates the intermediate insulating layer and has a second width greater than the first width.