3D Memory Array Tier Structure for Gate-Last Electrical Isolation
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Solution Overview
Problem
Current memory array technologies face challenges in efficiently forming vertically-stacked memory cells with reliable electrical access and isolation, particularly in the 'gate-last' or 'replacement-gate' process, where achieving precise control over conductive and insulative tiers is crucial for maintaining data retention and storage efficiency.
Innovation Solution
The method involves forming a conductor tier with alternating insulative and conductive tiers, where channel-material strings extend through these tiers, and intervening material provides lateral isolation between memory blocks, with specific etching and deposition processes to ensure direct electrical coupling and optimal material composition for effective memory cell formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically-stacked memory cells are formed using gate-last or replacement-gate process, then data retention and storage efficiency are improved, but precise control over conductive and insulative tiers becomes more difficult to achieve
Solution Approach 1:
The memory array is divided into multiple memory blocks with alternating conductive and insulative tiers, allowing independent formation and control of each tier. This segmentation enables precise control over the conductive and insulative layers while maintaining the vertically-stacked architecture necessary for data retention.
Solution Approach 2:
Different materials and formation processes are applied to different tiers based on their specific functional requirements. Conductive tiers use materials optimized for electrical conduction while insulative tiers use materials with superior isolation properties, allowing each tier to be precisely controlled according to its local quality requirements.
2Reliability
If vertically-stacked memory cells are formed with alternating conductive and insulative tiers, then electrical access and isolation are improved, but device complexity increases
Solution Approach 1:
The alternating conductive and insulative tiers serve multiple functions simultaneously: conductive tiers provide electrical pathways for data access while insulative tiers provide electrical isolation between adjacent memory blocks. This multi-functionality reduces the need for separate dedicated structures, thereby managing complexity while improving electrical access and isolation.
Solution Approach 2:
The insulative tiers are positioned between and around the conductive tiers in a nested configuration, where each insulative tier is contained within the vertical structure defined by adjacent conductive tiers. This nesting approach allows compact integration of multiple functional layers without proportionally increasing overall device complexity.
3Productivity
If channel-material strings extend through multiple tiers with direct electrical coupling, then storage efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The channel-material strings are formed to extend through all tiers in advance, establishing continuous electrical pathways before final assembly and coupling operations. This preliminary formation of channel materials ensures that the strings are pre-positioned correctly, reducing the precision requirements for subsequent etching and deposition processes that establish direct electrical coupling.
Solution Approach 2:
The channel-material strings act as intermediary elements that facilitate electrical coupling between the vertically-stacked memory cells and the external circuitry. By using these intermediate conductive pathways, the direct coupling requirement is mediated through well-controlled channel material interfaces, reducing the overall manufacturing precision burden.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of memory arrays with improved data retention and storage efficiency by ensuring precise electrical access and isolation, enhancing the reliability and performance of vertically-stacked memory cells.
Implementation Method 1
The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers
Implementation Method 2
Conducting material is deposited into the trenches and into the void-space in the first tiers
Data Source
AI summary
A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Conducting material of a lowest of the conductive tiers is directly against the conductor material of the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The conducting material in the lowest conductive tier is directly against the channel material of individual of the channel-material strings. Conductive material is of different composition from that of the conducting material above and directly against the conducting material. Other embodiments, including method, are disclosed.