3D Memory Stack Layout With Split Arrays and Tiered Periphery
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Solution Overview
Problem
The demand for increased memory capacity is hindered by the limitations of planar memory cells, which become challenging and costly to scale further, while 3D memory architectures face challenges in integrating high-density storage with fast read and write speeds and low power consumption.
Innovation Solution
A 3D memory device is formed by creating an array of through stack structures with a slit structure to separate different types of memory cells, and bonding peripheral circuits at different levels to reduce chip size and increase memory density, utilizing hybrid bonding and transfer bonding techniques to integrate ferroelectric and NAND memory cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell scaling to three-dimensional stacked memory architecture. Multiple memory cell arrays are stacked vertically with peripheral circuits positioned at different levels (first level and second level), enabling increased memory density without further reducing feature sizes and avoiding the associated manufacturing complexity and cost increases.
2Quantity of substance
If 3D memory architecture is implemented, then memory density is improved, but integration of high-density storage with fast read/write speeds and low power consumption becomes challenging
Solution Approach 1:
The patent segments the memory device into distinct functional regions: first memory cell arrays, second memory cell arrays, and peripheral circuits, each positioned at different vertical levels. This segmentation allows independent optimization of each component for its specific function while maintaining high-density 3D integration, enabling both high memory density and reliable operational performance.
Solution Approach 2:
By arranging memory cell arrays and peripheral circuits in three-dimensional space at different vertical levels rather than planar arrangement, the patent achieves high memory density while maintaining short interconnect lengths for fast read/write speeds and enabling efficient power distribution for low power consumption.
3Device complexity
If peripheral circuits are integrated at the same level as memory cell arrays, then device complexity is reduced, but chip size increases
Solution Approach 1:
The patent positions peripheral circuits at different vertical levels relative to memory cell arrays - some peripheral circuits at a first level and others at a second level. This three-dimensional integration reduces the lateral chip area required while maintaining functional integration, as vertical stacking replaces horizontal expansion.
Data Source
AI summary
Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first-type through stack structures in a first region and an array of second-type through stack structures in a second region, and a slit structure separating the array of first-type through stack structures from the array of second-type through stack structures. The 3D memory device further includes a second semiconductor structure. The second semiconductor structure includes a first periphery circuit and a second periphery circuit at different levels. The second semiconductor structure and the first semiconductor structure are bonded together, such that the first periphery circuit is located between the second periphery circuit and the first semiconductor structure.