3D Memory Cell Stack With TLV Interconnects for Dense Arrays
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and are hindered by the large size of Through Silicon Vias (TSVs) which restrict the number of connections that can be made in 3D ICs.
Innovation Solution
The development of a method for producing 3D semiconductor devices using a multilayer structure with Through Layer Vias (TLVs) of less than 400 nm diameter, allowing for the creation of multiple independent memory arrays and enabling the use of 3D IC technology in various device applications by reducing the size of interconnects through the integration of configurable logic, memory, and I/O dies with Through-Silicon-Via connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Through Silicon Vias (TSVs) are used for 3D IC connections, then vertical interconnect is achieved, but the large size of TSVs restricts the number of connections that can be made
Solution Approach 1:
The patent transitions from conventional planar 2D interconnects to three-dimensional vertical interconnects using TSVs and TLVs. This dimensional change enables connections through the thickness of the substrate, dramatically increasing the number of possible connections per unit area by utilizing the vertical dimension for signal routing between stacked dies.
Solution Approach 2:
The patent evolves the interconnect structure from large-diameter TSVs to smaller-diameter TLVs (less than 400 nm). This parameter change in via diameter allows for higher density of interconnects, enabling more connections to be made in the same area while maintaining electrical performance.
2Adaptability or versatility
If conventional fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent divides the fabrication process into distinct modules: forming TSVs/TLVs, depositing metal layers, creating isolation structures, and forming active devices. Each module can be independently optimized and reused across different device configurations, reducing overall process complexity and enabling greater flexibility in product design.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the TSV/TLV structures and isolation layers before device fabrication. This preliminary structuring establishes a flexible foundation that allows subsequent processing steps to be adapted for different logic families and device types without requiring complete process reconfiguration.
Data Source
AI summary
A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, first transistors control power delivery to some second transistors; and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.