3D Memory Transistor Gate Voltage Control for Erase Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently managing voltage distributions during erase operations in three-dimensional memory structures, leading to potential transistor breakdowns due to uneven electric potentials across unselected memory blocks.
Innovation Solution
The semiconductor device incorporates a voltage supply circuit that applies a first positive voltage to the gates of unselected select transistors in unselected memory blocks during erase operations, using second voltage generation circuits to adjust voltages and prevent Gate Induced Drain Leakage (GIDL) current generation, thereby maintaining stable electric potentials and reducing the likelihood of transistor breakdowns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase voltage is applied to common source line during erase operation, then erase operation is performed on selected memory block, but electric potential difference causes transistor breakdown in unselected memory blocks
Solution Approach 1:
The patent applies a preliminary counter-voltage (first positive voltage) to the gates of first select transistors in unselected memory blocks before and during the erase operation. This preemptive action creates an opposing electric potential that counteracts the harmful voltage difference caused by applying erase voltage to the common source line, preventing transistor breakdown before it can occur.
Solution Approach 2:
The patent maintains equipotential conditions across unselected memory blocks by applying the first positive voltage to the gates of first select transistors. This equalizes the electric potential distribution during erase operations, eliminating the potential difference that would otherwise cause harmful effects in unselected blocks.
2Quantity of substance
If three-dimensional memory structure is used to increase memory cell density, then storage capacity increases, but voltage distribution management becomes complex
Solution Approach 1:
The patent segments the memory device into multiple independently controllable memory blocks, each with its own select transistors and voltage control circuitry. This segmentation allows selective application of erase voltage to only the target memory block while maintaining controlled potential in other blocks, simplifying voltage distribution management despite the three-dimensional structure.
Solution Approach 2:
The patent introduces intermediate voltage control circuits (voltage supply circuit and second voltage generation circuits) that act as mediators between the erase voltage source and the memory blocks. These intermediary circuits intelligently distribute voltages, applying erase voltage only to the selected block while providing compensating positive voltages to unselected blocks, thereby managing the complexity of voltage distribution in the three-dimensional structure.
3Reliability
If Gate Induced Drain Leakage (GIDL) current is prevented by voltage control, then transistor reliability improves, but additional voltage generation circuits are required
Solution Approach 1:
The voltage supply circuit and second voltage generation circuits serve multiple functions: they generate the first positive voltage to prevent GIDL current in unselected memory blocks, they also manage the overall voltage distribution during erase operations, and they maintain equipotential conditions across all memory blocks. This multi-functionality justifies the additional circuits by consolidating multiple voltage management tasks into unified circuitry.
Data Source
AI summary
A semiconductor device includes a plurality of memory blocks, wherein each of the plurality of memory blocks includes a first select transistor electrically coupled to a common source line, a second select transistor electrically coupled to a bit line, and a plurality of memory cells electrically coupled between the first and second select transistors, and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, and applying a first positive voltage to gates of the first select transistors in unselected memory blocks of the plurality of memory blocks when an erase voltage is applied to the common source line during the erase operation.