3D Semiconductor Memory Bonding to Protect Peripheral Transistors
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to expensive processing equipment needed for fine pattern formation, restricting their ability to store large amounts of data effectively.
Innovation Solution
A three-dimensional semiconductor memory device is developed with a peripheral circuit structure and cell array structure bonded through bonding pads, featuring vertical channel structures and a stack structure with gate electrodes, source conductive patterns, and data storage patterns, allowing for increased storage capacity per unit area while simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices are used to increase storage capacity, then integration level must be increased, but expensive processing equipment is required for fine pattern formation
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing storage capacity to increase without requiring finer lateral patterns. This dimensional change eliminates the need for expensive fine pattern processing equipment while achieving high integration.
2Reliability
If heat treatment processes are applied during fabrication, then material properties are improved, but peripheral transistors may be damaged
Solution Approach 1:
The device is divided into two separately fabricated structures: a cell array structure containing memory cells that undergo heat treatment, and a peripheral circuit structure containing transistors that are protected from heat treatment. The structures are then bonded together through bonding pads, allowing differential processing conditions for each segment.
Solution Approach 2:
The peripheral circuit structure is fabricated first with transistors formed before the heat treatment process. This preliminary formation of transistors in a separate structure allows them to be protected from subsequent high-temperature processing of the memory cell stack, preventing thermal damage while still achieving the desired material properties in the heat-treated regions.
3Ease of manufacture
If bonding pads are used to connect cell array and peripheral circuit structures, then manufacturing flexibility is improved, but bonding precision is required
Solution Approach 1:
The bonding pads are designed to self-align during the bonding process. The cell array structure is bonded to the peripheral circuit structure through these pads, which automatically position the two structures relative to each other, reducing the need for high-precision external alignment equipment and processes.
Data Source
AI summary
Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.