3D Memory Transistor Threshold Voltage Stabilization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory devices, the threshold voltages of select transistors in NAND strings can fluctuate due to read disturb stress, data retention loss, and process variations, leading to potential memory device failures if not accurately controlled.
Innovation Solution
A control circuit is implemented to maintain threshold voltages of non-data transistors in a three-dimensional memory device by testing and adjusting the voltages of select and dummy memory cell transistors within specified ranges, ensuring reliable memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If threshold voltage testing and adjustment operations are performed frequently to maintain select transistor threshold voltages, then memory device reliability is improved, but memory device performance and productivity deteriorate due to operation overhead
Solution Approach 1:
The patent performs threshold voltage maintenance operations proactively before they become critical. The system monitors threshold voltage drift and schedules testing and adjustment operations in advance, preventing failures rather than reacting to them. This preliminary action reduces the urgency and frequency of corrective operations, improving overall device performance while maintaining reliability.
Solution Approach 2:
The patent implements a feedback mechanism that continuously monitors threshold voltage levels of select transistors and adjusts maintenance operation timing based on actual drift conditions. The system uses measured threshold voltage data to dynamically determine when testing and adjustment operations are needed, optimizing the balance between reliability maintenance and performance preservation by avoiding unnecessary operations.
2Stability of the object's composition
If comprehensive threshold voltage testing and adjustment operations are performed on all non-data transistors, then threshold voltage stability is improved, but operation time and complexity increase
Solution Approach 1:
The patent applies threshold voltage maintenance operations selectively to specific non-data transistors based on their individual threshold voltage drift characteristics rather than uniformly to all transistors. The system identifies and targets only those transistors exhibiting significant drift, performing testing and adjustment operations locally where needed. This localized approach maintains threshold voltage stability for critical transistors while minimizing overall operation time and complexity.
3Reliability
If select transistor threshold voltages are tightly controlled within specified ranges, then memory device reliability is improved, but device complexity increases due to additional control operations
Solution Approach 1:
The patent implements a self-service mechanism where the memory system performs its own threshold voltage maintenance using integrated control circuits and testing operations. The system autonomously monitors, tests, and adjusts select transistor threshold voltages without requiring external intervention or complex external control systems. This self-service approach maintains tight threshold voltage control for reliability while managing device complexity through integrated, automated operations.
Data Source
AI summary
Techniques are provided for maintaining threshold voltages of non-data transistors in a memory device. The memory device has a stack comprising alternating horizontal conductive layers and horizontal dielectric layers. A control circuit is configured to test a threshold voltage criterion of non-data transistors in response to a trigger condition being met with respect to an erase of a data memory cells in a first tier of the stack. The control circuit is configured move valid data out of a data memory cells in a second tier of the stack in response to a determination that the threshold voltage criterion is not met. The control circuit is configured to adjust threshold voltages of the non-data transistors after moving the valid data out of the second set of data memory cells such that the threshold voltage criterion is met.