3D Memory Cell Structure With Trap-Suppressing Capping Layer
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Solution Overview
Problem
The miniaturization of memory cells in semiconductor devices limits the increase in memory cell density and capacitance due to structural constraints, making it difficult to reduce parasitic capacitance effectively.
Innovation Solution
A semiconductor device with a three-dimensional structure featuring vertically stacked memory cells, including a lower structure, active layer, bit line, word line, and capping layers with trap-suppressing materials like silicon oxide, which helps in reducing parasitic capacitance and increasing memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase net die, then memory cell density increases, but parasitic capacitance increases and capacitance decreases due to structural limitations
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking. Multiple memory cells are stacked along the vertical direction (third dimension) using through-silicon vias (TSVs) and interlayer dielectric structures, enabling increased memory cell density without increasing parasitic capacitance in the planar dimensions.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically. Each memory cell layer contains separate bit lines, word lines, and storage elements that are independently structured and connected through vertical interconnects, allowing density increase while managing parasitic effects through spatial separation.
2Area of stationary object
If memory cell size is reduced, then net die increases, but capacitance increases and leakage current increases due to structural constraints
Solution Approach 1:
Interlayer dielectric materials and barrier layers are introduced as intermediary structures between adjacent memory cell components. These intermediary layers provide electrical isolation and prevent direct contact between conductive elements, thereby reducing leakage current while enabling vertical integration for increased net die.
Solution Approach 2:
By moving to three-dimensional vertical stacking, the patent separates memory cell components in the vertical dimension rather than compressing them in the planar dimensions. This spatial separation in the third dimension reduces parasitic coupling and leakage current while increasing the effective net die area.
Data Source
AI summary
A semiconductor device includes: a lower structure; an active layer over the lower structure; a bit line coupled to one side of the active layer and extending vertically from the lower structure; a data storage element coupled to another side of the active layer; a word line disposed adjacent to the active layer and extending in a direction crossing the active layer; and a capping layer disposed between the word line and the data storage element and including a trap-suppressing material in contact with the active layer.