3D Memory Trapping Layer Thickness Optimization
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, conventional 3D memory architectures face challenges in electrical performance and manufacturing yield due to the increasing number of layers in the stack structure, making it difficult to achieve higher storage density.
Innovation Solution
A 3D memory device is designed with a trapping layer that has a greater thickness in its upper portion than in its lower portion, improving electrical performance by optimizing the thickness distribution and material composition of the trapping layer, and incorporating a blocking layer and tunneling layer to enhance charge trapping ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in the stack structure is increased to achieve higher storage density, then the storage capacity is improved, but the electrical performance and manufacturing yield deteriorate
Solution Approach 1:
The trapping layer is designed with non-uniform thickness, being thicker in the upper portion and thinner in the lower portion. This local variation in thickness allows different regions of the memory device to have optimized charge trapping characteristics, improving electrical performance while maintaining high storage density through the increased number of layers
Solution Approach 2:
The thickness parameter of the trapping layer is changed from uniform to non-uniform distribution. By adjusting the thickness parameter locally (thicker upper portion, thinner lower portion), the device achieves better electrical performance and manufacturing yield while maintaining high storage capacity through multiple layers
2Quantity of substance
If the number of layers in the stack structure is increased to achieve higher storage density, then the storage capacity is improved, but the manufacturing yield deteriorates
Solution Approach 1:
The non-uniform thickness distribution of the trapping layer (thicker upper, thinner lower) optimizes charge trapping efficiency locally, which improves manufacturing yield by reducing defects and variability in the manufacturing process while maintaining high storage density through multiple layers
Solution Approach 2:
By changing the thickness parameter of the trapping layer from uniform to non-uniform, the manufacturing process becomes more robust and yields improve, while the multi-layer structure maintains high storage capacity
3Manufacturing precision
If the thickness of the trapping layer is reduced in lower memory units, then the programming and erasing variations are improved, but the charge trapping capacity may be compromised
Solution Approach 1:
The trapping layer thickness is optimized locally: thinner in lower memory units to reduce programming and erasing variations, and thicker in upper portions to maintain sufficient charge trapping capacity. This local differentiation resolves the contradiction between precision and capacity
Solution Approach 2:
The trapping layer is segmented into different thickness regions (upper and lower portions) with each region optimized for its specific function. The lower portion is thinner for precision control, while the upper portion is thicker for adequate charge trapping, together providing both improved variations and maintained capacity
Data Source
AI summary
A three-dimensional (3D) memory device includes a substrate, an alternating conductive/dielectric stack disposed on the substrate, an epitaxial layer disposed on the substrate, a blocking layer disposed on the epitaxial layer and surrounded by the alternating conductive/dielectric stack, a trapping layer disposed on and surrounded by the blocking layer, a tunneling layer disposed on and surrounded by the trapping layer, and a semiconductor layer disposed on and in contact with the epitaxial layer and partially disposed on and surrounded by the tunneling layer.