3D Memory Trapping Sections for Reduced Cell Interference
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, conventional 3D memory architectures face challenges in electrical performance and manufacturing yield due to increasing layers and thinning structures, necessitating modifications in structure and manufacturing processes.
Innovation Solution
The 3D memory device incorporates trapping sections between semiconductor and gate material layers, with insulation layers and air voids between gate material layers, and a blocking layer surrounding the trapping and semiconductor layers, along with a manufacturing method that includes a second etching process to expose trapping layers and forms insulation layers alternately with sacrificial layers, replacing these with gate material layers and oxidizing epitaxial layers for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the amount of layers in the stack structure increases and each layer becomes thinner for higher storage density, then storage density is improved, but electrical performance and manufacturing yield deteriorate
Solution Approach 1:
The trapping layer is segmented into multiple discrete trapping sections along the vertical channel, with insulation layers positioned between adjacent trapping sections. This segmentation isolates electrical interference between different memory cell levels, maintaining electrical performance while enabling higher storage density through increased layer count.
Solution Approach 2:
Insulation layers are introduced as intermediary structures between adjacent trapping sections and between gate material layers. These insulation layers act as electrical mediators that prevent parasitic coupling and interference, thereby maintaining manufacturing yield and electrical performance despite the increased number of thin layers in the stack structure.
2Ease of manufacture
If trapping layers are continuously formed without insulation between adjacent sections, then manufacturing process is simplified, but electrical interference between memory units increases
Solution Approach 1:
The continuous trapping layer is divided into discrete trapping sections separated by insulation layers. This segmentation approach maintains relative manufacturing simplicity while effectively blocking electrical interference between adjacent memory units, as the insulation layers can be formed using standard deposition and patterning processes.
Solution Approach 2:
Insulation layers are extracted and positioned at specific locations between trapping sections where electrical interference would occur. This targeted extraction approach removes only the necessary portions to eliminate interference while preserving the overall manufacturing flow and minimizing additional process complexity.
3Quantity of substance
If gate material layers are placed closely together to increase density, then storage capacity is improved, but RC delay increases due to higher capacitance between layers
Solution Approach 1:
Insulation layers are positioned between adjacent gate material layers to act as electrical mediators. These intermediary layers reduce the parasitic capacitance between closely-spaced gate layers, thereby decreasing RC delay and allowing higher storage capacity through increased layer density without significant performance penalty.
Solution Approach 2:
Air voids are introduced within the insulation layers to create a porous structure. Since air has significantly lower dielectric constant than solid insulation material, this porous configuration further reduces the capacitance between gate material layers, minimizing RC delay while maintaining the high-density stacked architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces interference between memory units, enhances charge trapping and maintaining ability, and improves RC delay by minimizing capacitance between gate material layers, thereby improving the electrical performance and manufacturing yield of the 3D memory device.
Implementation Method 1
improves RC delay by minimizing capacitance between gate material layers
Implementation Method 2
a blocking layer surrounding the trapping layer and the semiconductor layer in the horizontal direction
Implementation Method 3
a part of the epitaxial layer is oxidized to be an oxide region
Data Source
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AI summary
A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The 3D memory device includes a substrate, insulation layers, gate material layers, and a vertical structure. The insulation layers and the gate material layers are disposed on the substrate and alternately stacked in a vertical direction. The vertical structure penetrates the gate material layers in the vertical direction. The vertical structure includes a semiconductor layer and a trapping layer. The semiconductor layer is elongated in the vertical direction. The trapping layer surrounds the semiconductor layer in a horizontal direction. The trapping layer includes trapping sections aligned in the vertical direction and separated from one another. The electrical performance of the 3D memory device may be improved by the trapping sections separated from one another.