3D Memory Device Trench Capacitor Integration
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Solution Overview
Problem
Conventional memory devices require a larger layout area due to the peripheral placement of capacitors, limiting the size reduction of memory devices.
Innovation Solution
A three-dimensional memory device with a trench capacitor is integrated into a gate stacked structure, where the capacitor is positioned within the memory array region, allowing for a reduced layout area by utilizing a gate stacked structure with channel holes and capacitor trenches, and a manufacturing method that forms the trench capacitor within this structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the capacitor is disposed in a peripheral region adjacent to the memory array region, then the memory device can be manufactured with conventional layout, but the layout area becomes larger and the device size cannot be reduced
Solution Approach 1:
The patent merges the capacitor structure with the gate stacked structure by forming the capacitor within the same trench as the memory cell. The gate stacked structure serves dual purposes: as the memory cell structure and as the capacitor structure, eliminating the need for separate peripheral capacitor regions and reducing overall layout area.
Solution Approach 2:
The patent transitions from a planar layout where capacitors are placed in peripheral regions to a vertical three-dimensional structure where capacitors are integrated within the gate stacked structure. This dimensional change allows capacitors to share the same footprint area as memory cells, significantly reducing the required layout area.
2Area of stationary object
If the capacitor is integrated into the gate stacked structure, then the layout area is reduced and device size is minimized, but the manufacturing process becomes more complex
Solution Approach 1:
The patent segments the trench formation process into distinct stages: forming the initial trench, forming the charge storage structure on the trench sidewall, and then forming the capacitor electrode and dielectric layers. This segmentation allows each component to be manufactured independently with optimized processes, reducing overall manufacturing complexity despite the integrated structure.
Solution Approach 2:
The patent performs preliminary actions by first forming the charge storage structure on the trench sidewall before forming the capacitor components. This preliminary formation of the charge storage structure serves as a foundation for subsequent capacitor manufacturing steps, streamlining the overall process and reducing complexity.
3Ease of manufacture
If the capacitor is placed in the peripheral region, then the manufacturing process is simpler, but the capacitance density is reduced and more area is required for the same storage capacity
Solution Approach 1:
The patent implements a nested structure where the capacitor components (electrode, dielectric layer) are nested within the gate stacked structure trench. The charge storage structure is formed on the trench sidewall, and the capacitor is integrated within the same vertical space, maximizing the use of available space and increasing capacitance density without requiring additional peripheral area.
Data Source
AI summary
Provided are a three-dimensional (3D) memory device and a manufacturing method thereof. The 3D memory device includes a gate stacked structure, a channel layer, a charge storage structure, an electrode layer and a capacitor dielectric layer. The gate stacked structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The gate stacked structure has at least one channel hole and at least one capacitor trench. The channel layer is disposed on the sidewall of the at least one channel hole. The charge storage structure is disposed between the channel layer and the sidewall of the at least one channel hole. The electrode layer is disposed on the sidewall of the at least one capacitor trench. The capacitor dielectric layer is disposed between the electrode layer and the sidewall of the at least one capacitor trench.