3D Memory Device Trench Formation via Channel-Last Method
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in achieving high memory cell density and preventing device failure due to high aspect ratios in three-dimensional (3D) memory device fabrication, particularly in forming trenches that are close to each other without causing the layer stack to collapse or leading to bit line/source line bridging.
Innovation Solution
A channel-last method is employed for forming 3D memory devices, where a layer stack with alternating dielectric materials is formed over a substrate, trenches are created, and the second dielectric material is replaced with conductive material to form word lines, lined with ferroelectric material, and then filled with a third dielectric material. Bit and source lines are formed, and portions of the third dielectric material are removed to create openings for channel material formation along the sidewalls, which are then filled with a fourth dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If trenches are formed close to each other to increase memory cell density, then memory cell density is improved, but the layer stack collapses or twists due to high aspect ratio
Solution Approach 1:
The patent divides the trench formation process into multiple stages: first forming word line trenches, then forming bit line trenches, and finally forming source line trenches. This segmentation allows each trench type to be formed with optimized spacing and support structures, preventing layer stack collapse while achieving high memory cell density.
Solution Approach 2:
The patent performs preliminary actions by forming sacrificial mandrels and support structures before forming the actual trenches. These preliminary structures provide mechanical support during subsequent processing steps, preventing layer stack twisting and collapse when trenches are formed close together.
2Area of stationary object
If trenches are formed with high aspect ratio to reduce device area, then device area is reduced, but bit line/source line bridging occurs
Solution Approach 1:
The patent segments the conductive line formation into separate steps for bit lines and source lines, with intermediate dielectric material formation between them. This segmentation prevents bridging by ensuring proper isolation and spacing, even when trenches have high aspect ratios.
Solution Approach 2:
The patent introduces intermediate dielectric materials and sacrificial mandrels as mediators during the trench formation process. These intermediary structures maintain proper spacing between bit lines and source lines, preventing bridging while allowing high aspect ratio trenches to be formed.
3Ease of manufacture
If conventional trench formation method is used, then manufacturing process is simple, but device failure occurs due to layer stack collapse
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial mandrels, support structures, and intermediate dielectric layers before forming the final trenches. These preliminary structures prevent layer stack collapse during processing, significantly improving device reliability while adding manageable process steps.
Solution Approach 2:
The patent introduces cushioning structures in the form of intermediate dielectric materials and support layers that are formed beforehand to protect the layer stack from collapsing during subsequent high aspect ratio trench formation and filling operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for high-density memory cell formation without collapsing or twisting issues, reduces contact resistance, and avoids bit line/source line bridging, enhancing device reliability and performance.
Implementation Method 1
lining sidewalls and bottoms of the trenches with a ferroelectric material
Data Source
AI summary
A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric.