3D Memory Source-Level Structure for Controlled Isolation Trench Depth
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Solution Overview
Problem
Current three-dimensional semiconductor devices face challenges in achieving controlled lateral isolation trench depth, which affects the electrical characteristics and reliability of vertical NAND strings due to variations in p-n junction heights and gate-induced-drain leakage current.
Innovation Solution
A method involving the formation of a three-dimensional memory device with a lower source-level semiconductor layer having varying thicknesses, an alternating stack of insulating and sacrificial layers, and lateral isolation trenches, where the sacrificial layers are replaced with source contact layers and electrically conductive layers to control trench depth and enhance electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lateral isolation trenches are formed to improve electrical isolation, then gate-induced-drain leakage is reduced, but control over trench depth becomes difficult leading to variations in p-n junction heights
Solution Approach 1:
A sacrificial layer is introduced as an intermediary element during trench formation. This sacrificial layer is deposited conformally and then anisotropically etched to create lateral isolation trenches with controlled depths. The sacrificial layer acts as a depth stopper, ensuring uniform trench depths across the substrate and preventing variations in p-n junction heights, thereby resolving the contradiction between achieving good electrical isolation and maintaining precise trench depth control
Solution Approach 2:
The patent employs parameter changes by controlling the thickness and material properties of the sacrificial layer to precisely dictate trench depth. By adjusting the sacrificial layer thickness parameter, the trench depth is controlled, which in turn controls the p-n junction height. This parameter-based approach enables simultaneous achievement of reliable electrical isolation and precise manufacturing control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of lateral isolation trench depth, reducing channel cut-off failures and gate-induced-drain leakage, thereby improving the operational reliability and efficiency of the semiconductor device.
Implementation Method 1
replacing the source-level sacrificial layer with at least a source contact layer by providing an etchant that etches the source-level sacrificial layer through the lateral isolation trench
Implementation Method 2
providing a reactant that deposits the source contact layer through the lateral isolation trench
Data Source
AI summary
A memory device includes a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, the upper source-level semiconductor layer, and the source contact layer, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor layer having a surface segment that contacts the source contact layer. In one embodiment, the upper source-level semiconductor layer may be locally thickened to provide sufficient etch resistance during formation of a lateral isolation trench. In another embodiment, a sacrificial line trench fill structure may be employed as an etch stop structure during formation of a lateral isolation trench.