3D Memory Through Stair Contacts With Integrated Dummy Channel Patterning
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Solution Overview
Problem
Existing 3D memory device fabrication processes require separate patterns for forming dummy channel structures and through stair contacts (TSCs), leading to inefficient die usage and increased costs due to the need for distinct fabrication steps.
Innovation Solution
The proposed method forms TSCs and dummy channel structures using the same pattern, allowing for shared resources and simplifying the fabrication process by integrating their formation into a single step, thereby optimizing die usage and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate patterns are used for forming dummy channel structures and through stair contacts (TSCs), then the fabrication process can maintain structural integrity, but die usage efficiency decreases and fabrication costs increase
Solution Approach 1:
The patent combines the formation of dummy channel structures and through stair contacts (TSCs) into a single pattern definition step. The pattern includes both dummy channel regions and TSC regions, allowing simultaneous formation of both structures through one etching and filling process sequence, thereby improving die usage efficiency while maintaining structural integrity
Solution Approach 2:
The single integrated pattern serves multiple functions: it defines both dummy channel structures (which provide mechanical support and process alignment references) and through stair contacts (which provide electrical connections). This multi-functional pattern eliminates the need for separate pattern definitions and process steps
2Manufacturing precision
If separate fabrication steps are used for dummy channel structures and TSCs, then each structure can be optimized independently, but process complexity and costs increase
Solution Approach 1:
The patent merges the fabrication steps for dummy channel structures and TSCs into a unified process flow. The same pattern definition, etching, and filling operations are used for both structures, reducing process complexity while maintaining manufacturing precision through consistent process parameters
3Area of stationary object
If multiple patterns are placed on the die, then die area utilization improves, but fabrication process time increases
Solution Approach 1:
The patent combines multiple pattern functions into a single pattern layout that can be placed on the die. This integrated pattern includes both dummy channel and TSC definitions, allowing high die area utilization while requiring only one fabrication process cycle, thus avoiding the time penalty of multiple separate processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances die efficiency by allowing additional patterns to be placed on the die, simplifies the fabrication flow, and reduces process costs by combining the formation of TSCs and dummy channel structures into a single process.
Implementation Method 1
A TSC in contact with the substrate is formed by depositing a conductor layer in the hollow core of the spacer
Data Source
AI summary
In an example, a three-dimensional (3D) memory device includes a memory stack and a through stair contact (TSC). The memory stack includes interleaved conductive layers and dielectric layers. The memory stack includes stairs in a staircase region. The TSC extends through the memory stack in the staircase region. The TSC includes a first conductor layer and a first spacer circumscribing the first conductor layer. The first conductor layer of the TSC is insulated from the conductive layers of the memory stack by the first spacer.