3D Memory Device Fabrication via Vertical Stacking and TSV Bonding
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and limited flexibility, particularly in constructing commercially viable logic families with diverse products, and they struggle with reducing inter-chip interconnects, which dominate IC performance and power consumption.
Innovation Solution
The development of a method for fabricating 3D Integrated Circuit (IC) devices using a layered structure with Through Silicon Via (TSV) connections, allowing for the creation of configurable logic devices with multiple layers and mixed-process dies, and employing antifuse technology for power management and interconnection, enabling smaller, more efficient connections and reducing the need for multiple mask sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is limited
Solution Approach 1:
The patent segments the semiconductor fabrication process into multiple independent levels (first level, second level, third level, fourth level) that can be manufactured separately and then bonded together. This allows different mask sets to be used for different levels, reducing the need for a single complex mask set and enabling modular manufacturing that lowers overall costs and increases flexibility.
Solution Approach 2:
The patent transitions from planar 2D fabrication to 3D vertical stacking by adding multiple levels bonded through Through Silicon Via (TSV) connections. This dimensional change allows logic families to be constructed in the vertical dimension rather than requiring extensive lateral mask patterns, reducing mask-set complexity while enabling diverse product configurations.
2Device complexity
If conventional planar IC structure is used, then fabrication is simpler, but inter-chip interconnects are large and dominate performance and power consumption
Solution Approach 1:
The patent stacks multiple functional levels vertically and connects them through TSVs, reducing interconnect length from millimeter-scale lateral connections in planar ICs to micrometer-scale vertical connections through the silicon substrate. This dramatically reduces interconnect length, improving performance and reducing power consumption while maintaining fabrication feasibility through established bonding processes.
Solution Approach 2:
The patent embeds multiple functional blocks (memory cells, transistors, interconnects) within each other in a vertical hierarchy, with lower levels nested beneath upper levels. This nesting approach compactly integrates multiple functions into a single chip volume, reducing the need for large external inter-chip interconnects and improving overall device density and performance.
3Adaptability or versatility
If multiple mask sets are used for diverse products, then product variety increases, but manufacturing cost increases
Solution Approach 1:
The patent divides the device into standardized modular levels that can be configured in different combinations to create diverse products. Each level can be manufactured with a standard mask set, and product variety is achieved by selecting and bonding different levels together, rather than requiring unique mask sets for each product variant. This segmentation enables cost-effective mass production of diverse logic families.
Solution Approach 2:
The patent designs each level with universal interfaces and standardized TSV configurations that can be used across multiple product types. A single level design can serve multiple functions depending on which levels are bonded together and how they are configured, enabling one mask set to support multiple products and reducing the total number of mask sets required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by minimizing the number of mask sets required and enhances IC performance by reducing interconnect size and complexity, enabling the production of a range of products with improved logic, memory, and analog functions while optimizing power usage.
Implementation Method 1
performing a first etch step comprising etching holes within said second level; performing a second etch step comprising etching holes within said third level
Implementation Method 2
said first etch step is directly followed by a first deposition of tunneling dielectric and then a second deposition comprising polysilicon
Implementation Method 3
performing a bonding of a fourth level above said third level, wherein said fourth level comprises a second single crystal layer
Data Source
AI summary
A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; and performing a bonding of a fourth level above the third level, where the fourth level includes a second single crystal layer, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having a same doping type.