3D Memory Circuit With TSV Data Lines for Higher Capacity
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Solution Overview
Problem
The end of Moore's law has been reached, limiting the number of transistors that can be defined on a semiconductor substrate, necessitating advancements to increase transistor density on IC chips.
Innovation Solution
A three-dimensional (3D) circuit design with multiple stacked IC dies, featuring memory circuits spanning across two or more dies, utilizing z-axis connections such as through silicon vias (TSVs) for direct electrical connections between overlapping memory blocks, and including addressing and input/output circuits on different dies to enhance data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory blocks are integrated on a single IC die, then memory capacity increases, but transistor density reaches maximum limits according to Moore's law
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by stacking multiple IC dies in the z-axis direction. Each die contains memory blocks, and the stacked configuration allows memory capacity to scale vertically rather than being constrained by the maximum transistor density on a single die surface.
Solution Approach 2:
The memory system is divided into multiple independent memory blocks distributed across different IC dies. Each die can be fabricated separately and then stacked, allowing independent optimization of each die while achieving overall high memory capacity through the combination of multiple segmented units.
2Quantity of substance
If memory blocks are distributed across multiple IC dies, then memory capacity exceeds single-die limits, but inter-die connection complexity increases
Solution Approach 1:
The global data lines on each die serve multiple functions: they connect to multiple memory blocks on the same die and also connect to corresponding data lines on adjacent dies through TSVs. This multi-functional design reduces the need for dedicated inter-die connection structures, simplifying the overall connection architecture.
Solution Approach 2:
The patent merges local data lines with global data lines by having them share the same physical conductors. Local data lines within a memory block are extended to become global data lines that traverse the die and connect to other dies, eliminating the need for separate local and global interconnect structures.
3Adaptability or versatility
If standard interfacing protocols are used for inter-die connections, then compatibility is maintained, but data throughput is limited by protocol overhead
Solution Approach 1:
The patent extracts and eliminates the intermediate interfacing protocol layer between dies by implementing direct native signal connections through TSVs. Data signals are transferred directly from one die to another without being converted to standard interface protocols and back, removing protocol overhead and enabling higher data throughput.
4Quantity of substance
If data lines are extended across multiple dies, then memory addressable space increases, but connection length and signal delay increase
Solution Approach 1:
The patent reduces data line connection length by transitioning from horizontal routing across large single dies to vertical routing through thin TSVs between stacked dies. The z-axis connection length through TSVs is much shorter than horizontal routing would require, reducing signal delay while maintaining large addressable memory space through the stacked configuration.
Data Source
AI summary
Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets. The z-axis connections in some embodiments electrically connect circuit nodes in overlapping portions of the first and third IC dies, and overlapping portions of second and third IC dies, in order to carry data between the third set of data lines on the third IC die and the first and second set of data lines of the first and second of memory block sets on the first and second IC dies. These z-axis connections between the dies are very short as the dies are very thin. For instance, in some embodiments, the z-axis connections are less than 10 or 20 microns. The z-axis connections are through silicon vias (TSVs) in some embodiments.