3D Memory Circuit With TSV Data Lines for Higher Density
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Solution Overview
Problem
The limitations of Moore's Law, which predicts a doubling of transistors on an IC die every two years, are nearing an end as the maximum number of transistors that can be defined on a semiconductor substrate is approached, necessitating alternative advancements for increased transistor density.
Innovation Solution
A three-dimensional (3D) circuit design featuring multiple stacked IC dies with a memory circuit spanning two or more dies, utilizing z-axis connections, such as through silicon vias (TSVs), to facilitate data transfer between dies, thereby increasing transistor density beyond traditional two-dimensional limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-dimensional IC die design is used, then manufacturing process is simple, but transistor density reaches maximum limit
Solution Approach 1:
The patent transitions from traditional two-dimensional IC die design to three-dimensional stacked die architecture. Multiple IC dies are stacked vertically and interconnected through z-axis connections (TSVs), enabling transistor density to increase by utilizing the vertical dimension rather than being constrained to the horizontal plane alone.
Solution Approach 2:
The memory circuit is divided into multiple memory blocks distributed across different stacked dies. Each die contains specific memory blocks, and the system uses segmentation to distribute memory capacity across multiple physical units, allowing increased overall density while maintaining manageable complexity for each individual die.
2Quantity of substance
If multiple memory blocks are distributed across stacked dies, then memory capacity increases, but data transfer complexity increases
Solution Approach 1:
The patent introduces z-axis connections (through-silicon vias or TSVs) as intermediary structures that enable direct vertical data transfer between stacked dies. These TSVs serve as mediators that simplify the data transfer architecture by providing dedicated vertical pathways, reducing the complexity that would otherwise arise from routing data across multiple horizontal interconnect layers.
Solution Approach 2:
The z-axis connection structure serves multiple functions: it provides mechanical support for stacking, enables electrical interconnection between dies, and facilitates data transfer between memory blocks on different dies. This multi-functionality reduces overall system complexity compared to using separate structures for each purpose.
3Quantity of substance
If z-axis connections are used to connect stacked dies, then transistor density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment features and registration marks during the die fabrication process, before stacking occurs. These preliminary actions establish precise alignment references that guide the stacking process, ensuring that z-axis connections (TSVs) on adjacent dies align correctly without requiring extremely tight process control during assembly.
Solution Approach 2:
The design includes self-aligning features where structural elements on one die automatically position themselves relative to corresponding elements on adjacent dies during the stacking process. This self-service alignment mechanism reduces the precision requirements for external alignment processes and minimizes the need for high-precision manufacturing equipment.
Data Source
AI summary
Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets. The z-axis connections in some embodiments electrically connect circuit nodes in overlapping portions of the first and third IC dies, and overlapping portions of second and third IC dies, in order to carry data between the third set of data lines on the third IC die and the first and second set of data lines of the first and second of memory block sets on the first and second IC dies. These z-axis connections between the dies are very short as the dies are very thin. For instance, in some embodiments, the z-axis connections are less than 10 or 20 microns. The z-axis connections are through silicon vias (TSVs) in some embodiments.