3D Semiconductor Memory Fabrication via Segmented TSV Formation
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and struggle with the integration of multiple memory layers and interconnects in 3D ICs due to large Through Silicon Via (TSV) sizes.
Innovation Solution
The development of a method for fabricating 3D ICs using a re-programmable antifuse with Through Silicon Via (TSV) technology, allowing for the construction of configurable logic, memory, and I/O dies with smaller, high-density connections, and incorporating layer transfer techniques to reduce the size and cost of TSVs, enabling more efficient 3D IC manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional Through Silicon Via (TSV) technology is used for integrating multiple memory layers, then connection density is limited, but manufacturing cost and complexity increase
Solution Approach 1:
The patent divides the TSV formation process into multiple stages: forming initial TSVs in the substrate, then forming additional TSVs in intermediate layers, and finally forming through-layer vias to connect all levels. This segmentation allows incremental construction of the 3D IC structure, reducing the complexity of forming all connections in a single step while achieving high connection density.
Solution Approach 2:
The patent transitions from traditional 2D IC interconnection to 3D vertical interconnection by forming TSVs that extend through the substrate and intermediate layers. This dimensional change enables connections between multiple memory layers stacked vertically, significantly increasing connection density while the modular layer-by-layer formation approach manages the manufacturing complexity.
2Ease of manufacture
If larger TSV sizes are used for integrating multiple memory layers, then manufacturing is easier, but connection density and performance decrease
Solution Approach 1:
The patent segments the TSV formation into multiple batches: initial TSVs with larger dimensions formed first for ease of manufacture, followed by additional TSVs and through-layer vias with progressively smaller dimensions. This allows the fabrication process to start with easier, larger features while achieving high overall connection density through multiple formation steps.
Solution Approach 2:
The patent performs preliminary TSV formation in the substrate before forming the intermediate layers and additional TSVs. This preliminary action establishes the foundation connections with larger, easier-to-manufacture dimensions, while subsequent TSVs with smaller dimensions are formed to achieve the required high connection density without compromising manufacturing ease for the initial structures.
3Adaptability or versatility
If diverse logic families with multiple products are produced, then market flexibility increases, but mask-set costs increase
Solution Approach 1:
The patent segments the logic family production into a common foundation layer with shared control circuits and interconnects, followed by multiple product-specific memory layer configurations. This allows diverse logic families to share the expensive mask sets for the foundation structures, while only requiring additional mask sets for the variable memory layers, thereby reducing overall mask-set costs while maintaining product diversity.
Solution Approach 2:
The patent creates a universal foundation structure with control circuits and interconnect layers that can support multiple different memory layer configurations. This universal foundation allows the same mask sets to be reused across diverse logic families and product variants, reducing mask-set costs while enabling market flexibility through different memory layer arrangements.
Data Source
AI summary
A method for producing a 3D memory device, the method comprising: providing a first level comprising a first single crystal layer; forming first alignment marks and control circuits comprising first single crystal transistors, wherein said control circuits comprise at least two metal layers; forming at least one second level above said control circuits; performing a first etch step within said second level; forming at least one third level above said at least one second level; performing a second etch step within said third level; and performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein said first etch step comprises performing a lithography step aligned to said first alignment marks.