3D Memory Cell Stack With TSV Interconnects and Modular Die Integration
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and limited flexibility, particularly in constructing commercially viable logic families with diverse products, and they struggle with reducing inter-chip interconnects which dominate IC performance and power consumption.
Innovation Solution
The development of a 3D IC technology using Through-Silicon Via (TSV) connections and a modular approach with configurable logic dies, memory dies, and analog dies, allowing for mixing and matching different process-manufactured dies, and incorporating antifuse layers for programmable interconnects to reduce the need for multiple mask sets and enhance connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If current semiconductor fabrication methods with multiple mask sets are used, then manufacturing precision can be maintained, but manufacturing costs increase and flexibility decreases
Solution Approach 1:
The patent segments the semiconductor fabrication process into modular components: standard logic die, memory die, and analog die that can be independently manufactured using standard mask sets, then combined through TSV connections to create customized products. This segmentation allows each module to be produced with conventional manufacturing techniques while the final integration provides product flexibility.
Solution Approach 2:
The patent creates universal interface structures (TSV connections and antifuse layers) that enable different types of dies (logic, memory, analog) manufactured with standard processes to be interconnected. This universal connection method allows the same fabrication approach to serve multiple product configurations, reducing the need for custom mask sets.
2Use of energy by moving object
If traditional planar IC structures are used, then manufacturing processes are simple, but interconnect length increases leading to higher power consumption and reduced performance
Solution Approach 1:
The patent transitions from traditional planar (2D) interconnect structures to three-dimensional vertical interconnects using Through-Silicon Vias. This dimensional change allows signals and power to be transmitted vertically through the substrate, dramatically reducing interconnect length and associated power consumption while enabling more compact device layouts.
3Adaptability or versatility
If multiple custom mask sets are created for diverse logic families, then product versatility is improved, but manufacturing costs and process complexity increase
Solution Approach 1:
The patent performs preliminary actions by pre-manufacturing standardized logic die, memory die, and analog die using conventional mask sets before final product assembly. These pre-fabricated modules contain all necessary logic functions that can be selectively combined, allowing product diversity to be achieved through configuration rather than custom fabrication.
Solution Approach 2:
The patent introduces antifuse layers as intermediary elements between different die types. These antifuse structures serve as programmable interconnect mediators that can be configured after fabrication to establish connections between logic, memory, and analog modules, enabling product customization without requiring custom mask sets for each configuration.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.