3D Memory Cell Stack With Programmable TSV Interconnects
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Solution Overview
Problem
Existing semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of diverse semiconductor devices with varying logic, memory, and I/O configurations.
Innovation Solution
The use of multilayer 3D IC devices with Through Silicon Vias (TSVs) and antifuse programmable interconnects allows for the construction of configurable logic devices, reducing mask-set costs and enabling flexible integration of logic, memory, and I/O configurations through modular and re-programmable designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent segments the semiconductor device into multiple functional layers including logic circuits, memory circuits, and I/O circuits that can be independently configured. This segmentation allows different portions of the device to be optimized and manufactured separately, then integrated together, thereby reducing mask-set costs while maintaining flexibility in configuration.
Solution Approach 2:
The patent transitions from traditional planar 2D layout to a 3D stacked architecture with multiple levels of circuits connected through vertical interconnects. This dimensional change enables greater configuration flexibility and reduces the number of mask sets required by allowing circuits to be distributed across multiple vertical layers rather than requiring complex planar routing.
2Adaptability or versatility
If diverse semiconductor devices with varying configurations are produced, then flexibility is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent implements a universal interconnect structure that can accommodate various circuit configurations through programmable logic and configurable routing. The same basic manufacturing process and interconnect architecture can support different logic, memory, and I/O configurations, reducing manufacturing complexity while enabling configuration diversity.
Solution Approach 2:
The patent incorporates programmable logic and configurable interconnect elements that can be programmed after manufacturing to achieve different device configurations. This dynamic reconfigurability allows a single manufactured device to adapt to multiple applications, reducing the need for complex re-manufacturing processes for different configurations.
3Productivity
If Through Silicon Vias are used for interconnects, then vertical integration is achieved, but interconnect size and TSV usage efficiency need optimization
Solution Approach 1:
The patent implements a nested interconnect structure where multiple levels of metal interconnects are integrated within and around the TSVs. This nesting allows efficient use of vertical space, enabling multiple signal paths and power/ground networks to share the same TSV infrastructure, thereby improving TSV usage efficiency while managing interconnect complexity.
Solution Approach 2:
The patent utilizes the vertical dimension extensively by stacking multiple interconnect layers and circuit levels above and below each other, connected through TSVs. This 3D interconnect architecture improves productivity by enabling shorter signal paths and higher density compared to planar layouts, while systematic design rules manage the resulting structural complexity.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors each of which includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors and overlaying the second metal layer, each of first memory cells include at least one second transistor; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors and overlaying the third level, each of second memory cells include at least one fourth transistor, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one of the second transistors includes a hafnium oxide gate dielectric.