3D Semiconductor Memory Device Fabrication via Modular TSV Integration
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through-Silicon Vias (TSVs) that restrict the number of connections that can be made.
Innovation Solution
The development of a method for constructing 3D ICs using a modular approach with Through-Silicon-Via (TSV) technology, allowing for the creation of configurable logic, memory, and I/O dies with smaller, more efficient connections, and incorporating antifuse layers for power management and interconnects, enabling the use of layer transfer techniques to achieve high-density connections and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The fabrication process is divided into separate modules: a first module for forming control circuits on a first substrate, and a second module for forming memory cells on a second substrate. These modules can be independently fabricated and then combined, allowing different process optimizations for each function while reducing overall mask-set requirements.
Solution Approach 2:
The invention creates a universal fabrication approach where the same basic process steps can be used to form different device types (control circuits and memory cells) on different substrates, which are then integrated into a single 3D IC structure, reducing the need for separate mask sets for each device type.
2Device complexity
If existing 3D IC technologies are used, then 3D integration is achieved, but Through-Silicon Vias are large which restricts number of connections
Solution Approach 1:
The invention transitions from planar 2D integration to true 3D vertical integration by stacking memory substrate over logic substrate with TSVs providing through-silicon interconnects. This third dimension enables significantly higher connection density compared to lateral routing in 2D designs.
Solution Approach 2:
The patent optimizes TSV parameters including reducing TSV diameter, optimizing TSV spacing, and controlling TSV depth to achieve higher connection density. By carefully controlling these parameters, the number of connections per unit area is increased while maintaining structural integrity.
3Productivity
If modular approach with TSV technology is used, then connectivity is increased, but manufacturing complexity increases
Solution Approach 1:
The fabrication process is divided into separate modules: a first module for forming control circuits on a first substrate, and a second module for forming memory cells on a second substrate. These modules can be independently fabricated and then combined, allowing different process optimizations for each function while reducing overall mask-set requirements.
Data Source
AI summary
A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.