3D Non-Volatile Memory Tubular Shell Low-Current Design
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Solution Overview
Problem
Current flash memory systems face challenges in reducing the size and cost of memory cell arrays while managing leakage currents and parasitic currents during data reading and programming operations, especially in three-dimensional memory structures.
Innovation Solution
A three-dimensional memory array is designed with a tubular shell structure for non-volatile re-programmable memory elements, where the thickness of the shell controls electrical conductance, and a method involving a semiconductor substrate, vertical switching layers, and multi-layer structures with trenches and oxide spacer layers is used to form bit line pillars and read/write elements with reduced current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional flash memory cell structures are used, then manufacturing processes are simpler, but memory density and storage capacity are limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar memory cell arrays to a three-dimensional stacked architecture where multiple memory cell layers are vertically stacked above a semiconductor substrate. This dimensional transition enables significantly higher memory density by utilizing the vertical space, with each layer containing memory cells formed between bit line pillars and word lines at different vertical positions.
Solution Approach 2:
The memory cell structure is segmented into multiple discrete layers stacked vertically, with each layer containing complete sets of bit line pillars, word lines, and memory elements. This segmentation allows independent formation and optimization of each layer while achieving high overall density through the stacked configuration.
2Ease of manufacture
If thicker shell is used in memory elements, then manufacturing is easier, but electrical conductance control and resistive states are reduced
Solution Approach 1:
The patent utilizes controlled oxidation processes where the oxidation time, temperature, and environmental conditions are precisely adjusted to achieve the desired shell thickness. By changing oxidation parameters such as time duration and oxygen exposure, the shell thickness can be precisely controlled to optimize both electrical conductance and manufacturing feasibility.
Solution Approach 2:
An oxide spacer layer is introduced as an intermediary material during the formation process. This oxide spacer serves as a template and thickness reference that enables precise control of the final shell thickness. The oxide spacer is deposited with controlled thickness and subsequently used to define the dimensions of the memory element shell through etching and formation processes.
3Ease of manufacture
If conventional current paths are used, then manufacturing is simpler, but leakage currents and parasitic currents increase
Solution Approach 1:
The memory element employs a tubular shell structure with controlled wall thickness that acts as a flexible barrier to current leakage. The thin film shell provides sufficient electrical isolation to prevent parasitic currents while maintaining the structural integrity needed for device operation. The shell's thickness is optimized to block leakage paths without compromising the memory element's electrical function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low current operation with high resistive states, reducing leakage currents and parasitic currents, thereby enhancing the density and efficiency of memory storage while simplifying manufacturing processes and reducing power consumption.
Implementation Method 1
The tubular shell has a thickness that controls an electrical conductance of the non-volatile re-programmable memory element across the bit line pillar and the word line
Implementation Method 2
depositing a layer of oxide spacer over the plurality of trenches
Data Source
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AI summary
A 3D nonvolatile memory array has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a structure having a tubular shell of read/write material enclosing an oxide core. In a rectangular form, one outer surface portion of the structure contacts the word line and another outer surface portion contacts the bit line. The thickness of the shell rather than its surface areas in contact with the word line and bit line determines the conduction cross-section and therefore the resistance. By adjusting the thickness of the shell, independent of its contact area with either the word line or bit line, each read/write element can operate with a much increased resistance and therefore much reduced current. Processes to manufacture such a memory array are also described.