3D Semiconductor Memory Tunnel Insulating Layer Segmentation
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges in reducing manufacturing costs while maintaining reliability, as existing technologies are limited by the high cost of advanced equipment needed for fine pattern formation in two-dimensional devices.
Innovation Solution
A 3D semiconductor memory device is designed with a stack structure including gate electrodes, insulating layers, a channel structure, a charge storing layer, a tunnel insulating layer, and a blocking insulating layer, utilizing nitrogen-containing materials and high-k dielectric layers to improve retention and endurance characteristics, and a method of fabricating this device by alternately stacking sacrificial and insulating layers, forming channel holes, and sequentially depositing tunnel insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional semiconductor memory device is implemented, then integration density is improved, but manufacturing cost increases due to new process technology requirements
Solution Approach 1:
The tunnel insulating layer is segmented into multiple sub-layers (first tunnel insulating layer, second tunnel insulating layer, third tunnel insulating layer) with different materials and functions. This segmentation allows each layer to be optimized independently for specific purposes (charge injection, oxidation prevention, charge storage) while maintaining overall cost-effectiveness through the use of standard semiconductor materials and processes
Solution Approach 2:
The patent employs composite material structures in the tunnel insulating layer, combining silicon oxide, silicon nitride, and silicon oxynitride in specific sequences. This composite approach leverages the advantageous properties of each material (oxidation resistance of silicon nitride, charge storage of silicon oxynitride, interface quality of silicon oxide) to achieve improved retention and endurance without requiring entirely new material systems
2Ease of manufacture
If the tunnel insulating layer is simplified, then manufacturing cost is reduced, but retention and endurance characteristics deteriorate
Solution Approach 1:
Different regions of the tunnel insulating layer are assigned different local qualities through material composition variations. The first tunnel insulating layer (silicon oxide) provides high-quality interfaces for charge injection, the second tunnel insulating layer (silicon nitride) provides oxidation resistance and charge trapping, and the third tunnel insulating layer (silicon oxynitride) provides additional charge storage. This local quality differentiation ensures optimal performance at each interface while maintaining overall reliability
Solution Approach 2:
The second tunnel insulating layer (silicon nitride) is positioned between the first and third tunnel insulating layers to prevent oxidation of the high-k dielectric layer during subsequent processing steps. This beforehand cushioning approach proactively protects against potential degradation before it can occur, ensuring long-term retention and endurance characteristics without requiring additional protective measures
3Manufacturing precision
If advanced fine pattern forming technology is used, then manufacturing precision is improved, but equipment cost and manufacturing complexity increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. By stacking multiple gate electrodes and insulating layers vertically, the device achieves higher integration density without requiring finer lateral patterning. This dimensional change allows standard patterning equipment to be used while still achieving advanced node equivalent density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances retention and endurance characteristics of 3D semiconductor memory devices by optimizing the tunnel and blocking insulating layers, reducing charge trap sites, and preventing oxidation, thereby improving the reliability and cost-effectiveness of the manufacturing process.
Implementation Method 1
the second tunnel insulating layer may prevent the high-k dielectric layer from being oxidized during the curing process
Implementation Method 2
The high-k dielectric layer may have a charge trap site density smaller than that of the second tunnel insulating layer
Data Source
AI summary
Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.