3D Memory Device U-Shaped String Architecture

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Solution Overview

Problem

Existing 3D semiconductor memory architectures face limitations in compactness, which restrict further increases in data storage capacity per unit area.

Innovation Solution

A 3D memory device architecture featuring multiple groups of 'U'-shaped strings of memory cells with varying depths and lengths, interconnected by buried string portions, and controlled by source and bit line selectors, allowing for efficient data storage with reduced area requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional 2D memory structure is used, then manufacturing process is simple, but data storage capacity per unit area is limited

Engineering Contradiction:
Improvedata storage capacity per unit areaVSAvoidmemory block architecture complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from traditional 2D memory cell arrangement to a 3D architecture by introducing U-shaped strings that extend vertically through multiple substrate layers. Memory cells are stacked along the vertical dimension, with buried string portions connecting source and bit line selectors at different depths, thereby increasing storage capacity per unit area through spatial dimensionality expansion

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The U-shaped memory string structure nests multiple functional components within a compact geometry: the buried string portion is embedded in the substrate, while the source line selector side string portion and bit line selector side string portion rise vertically and are interconnected through shared control gates, creating a nested configuration that maximizes space utilization

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of stationary object

If memory blocks are compacted to increase storage density, then area is reduced, but electrical connectivity and control become more difficult

Engineering Contradiction:
Improvememory block areaVSAvoidelectrical connectivity
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The memory block is segmented into multiple U-shaped strings, each independently connected to source and bit line selectors through buried string portions. This segmentation allows parallel electrical pathways, where each string can be selectively activated, maintaining reliable connectivity while accommodating high density through modular organization of memory cells

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buried string portion acts as an intermediary element that establishes electrical connection between the source line selector and bit line selector through the substrate. This intermediate structure enables reliable signal transmission across compacted memory blocks by providing dedicated conduction paths that traverse the vertical depth of the device

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10411030B23D memory device
Publication Date: 2019.09.10 AVANEIDI SPA
  • US10411030B2 patent drawing
  • US10411030B2 patent drawing
  • US10411030B2 patent drawing

AI summary

A 3D memory device comprising: a substrate; at least one first group of at least three first U-shaped memory cells strings each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first U-shaped memory cells strings including memory cells stacks along the first source line selector side string portion and along the first bit line selector side string portion; and at least one second group of at least three second U-shaped memory cells strings each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion. The second buried string portion is formed in the substrate and connects the second source line selector side string portion and the second bit line selector side string portion, each of the second U-shaped memory cells strings including memory cells stacks along the second source line selector side string portion and along the second bit line selector side string portion. The first and second source line selector side string portions are between the first and second bit line selector side string portions. The at least three first U-shaped memory cells strings are mutually co-planar and one surrounded by the other, and the at least three second U-shaped memory cells strings are mutually co-planar and one surrounded by the other.