3D Memory U-Shaped Strings Staggered Layout
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Solution Overview
Problem
Existing 3D semiconductor memory architectures have limitations in compactness, which restrict further increases in data storage capacity per unit area.
Innovation Solution
A 3D memory device architecture featuring 'U'-shaped strings of memory cells with buried string portions of varying depths and lengths, arranged in a staggered and co-planar configuration to optimize space usage, along with source and bit line selectors, allowing for improved compactness and data storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory blocks are compacted to increase data storage capacity per unit area, then storage density improves, but the risk of string contact increases which compromises device reliability
Solution Approach 1:
The patent transitions from traditional 2D memory cell arrangement to a 3D configuration by forming U-shaped strings that extend vertically into the substrate with buried portions at different depths. This dimensional change allows memory cells to be stacked in multiple layers, increasing storage capacity per unit area while maintaining spatial separation between strings to prevent contact and ensure reliability.
Solution Approach 2:
The patent implements a nested arrangement where U-shaped strings are positioned within rectangular regions defined by word lines, with strings of different depths nested vertically. The buried string portions are embedded at varying depths in the substrate, creating a nested structure that maximizes space utilization while preventing string interference through depth-based separation.
2Area of stationary object
If U-shaped strings with varying buried string depths and lengths are used, then space utilization and compactness improve, but device complexity increases
Solution Approach 1:
The patent divides the memory block into multiple rectangular regions, each containing U-shaped strings with specific configurations. By segmenting the memory block and assigning different string depth/length patterns to different regions, the design achieves compactness through systematic variation while managing complexity through modular regional organization rather than uniform complex design throughout.
Solution Approach 2:
The patent applies local quality by varying the buried string depth and length characteristics in different rectangular regions of the memory block. Each region has optimized string configurations tailored to local spatial requirements, allowing compactness in densely populated areas while maintaining simplicity in other regions, thus achieving overall compactness without uniform complexity throughout the entire device.
Data Source
AI summary
A 3D memory device comprising: a substrate; at least one first group of four first “U”-shaped memory cells strings each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first “U”-shaped memory cells strings including memory cells stacks along the first source line selector side string portion and along the first bit line selector side string portion; and at least one second group of four second “U”-shaped memory cells strings each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion, wherein the second buried string portion is formed in the substrate and connects the second source line selector side string portion and the second bit line selector side string portion, each of the second “U”-shaped memory cells strings including memory cells stacks along the second source line selector side string portion and along the second bit line selector side string portion, wherein the first and second source line selector side string portions are between the first and second bit line selector side string portions, and wherein a first pair of the first “U”-shaped memory cells strings are mutually co-planar and one surrounded by the other, a second pair of the first “U”-shaped memory cells strings are mutually co-planar but staggered with respect to the first pair of first “U”-shaped memory cells strings and one surrounded by the other, a first pair of the second “U”-shaped memory cells strings are mutually co-planar and one surrounded by the other, a second pair of the second “U”-shaped memory cells strings are mutually co-planar but staggered with respect to the first pair of second “U”-shaped memory cells strings and one surrounded by the other.