3D Memory Cell Stacking With Unified Bonding for Reliability

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Solution Overview

Problem

The integration degree of semiconductor devices is limited by the area occupied by unit memory cells, and there is a need for improved operation reliability in three-dimensional semiconductor devices with stacked memory cells.

Innovation Solution

A semiconductor device structure is developed with alternating layers of insulating and conductive materials, including gate structures, stacks, channel structures, and contact plugs, which are formed and bonded to create a stable and reliable structure, reducing manufacturing costs by unifying the bonding structures in a single operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If memory cells are stacked in three-dimensional structure to improve integration degree, then area occupancy is reduced, but operation reliability deteriorates

Engineering Contradiction:
Improvearea occupancyVSAvoidoperation reliability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The semiconductor device is divided into multiple functional layers including first and second stacks, first and second gate structures, and first and second contact plugs. Each layer performs specific functions independently, allowing the three-dimensional structure to achieve high integration while maintaining operational reliability through modular design and functional separation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional planar memory cells to three-dimensional vertically-stacked memory cells. Multiple memory cell layers are stacked in the vertical dimension, significantly reducing area occupancy while maintaining reliable operation through proper structural design including alternating insulating and conductive layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Stability of the object's composition

If multiple bonding structures are formed separately to ensure structural stability, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvestructural stabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

Multiple bonding structures including source bonding structures and contact bonding structures are formed in a unified bonding process. The first and second contact plugs are simultaneously bonded to their respective bonding structures in a single operation, reducing manufacturing complexity while ensuring structural stability through integrated bonding.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bonding structures are designed to serve multiple functions: the first contact bonding structure bonds both the first contact plug and provides structural support, while the second contact bonding structure performs similar dual functions. This multi-functionality reduces the number of separate bonding operations required.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250351363A1Semiconductor device and method of manufacturing semiconductor device
Publication Date: 2025.11.13 SK HYNIX INC
  • US20250351363A1 patent drawing
  • US20250351363A1 patent drawing
  • US20250351363A1 patent drawing

AI summary

A semiconductor device may include a peripheral circuit, a first gate structure positioned on the peripheral circuit, a first stack positioned at a level corresponding to the first gate structure, a source bonding structure positioned on the first gate structure, a first contact bonding structure positioned on the first stack, first channel structures extending into the source bonding structure through the first gate structure, a first contact plug extending into the first contact bonding structure through the first stack, a second gate structure positioned on the source bonding structure, a second stack positioned on the first contact bonding structure, second channel structures extending into the source bonding structure through the second gate structure, and a second contact plug extending into the first contact bonding structure through the second stack.