3D Semiconductor Memory Devices With Variable Gate Dielectric Thickness
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited due to the need for expensive processing equipment to achieve fine pattern formation, restricting their reliability and integration density.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a substrate having a cell array region, peripheral circuit region, and connection region, featuring a horizontal gate dielectric layer with varying thicknesses and electrode structures stacked vertically, enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use fine pattern formation to increase integration, then integration density improves, but manufacturing cost increases due to expensive processing equipment
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell structures to three-dimensional vertically stacked structures. Multiple memory cells are stacked in the vertical direction, allowing integration density to increase without requiring finer lateral patterning. This dimensional change enables higher capacity while avoiding the need for expensive ultra-fine lithography equipment.
2Quantity of substance
If two-dimensional semiconductor memory devices increase pattern fineness to improve integration, then integration density improves, but manufacturing complexity increases due to expensive processing equipment
Solution Approach 1:
By stacking memory cells vertically in the third dimension, the patent achieves higher integration density without requiring increasingly complex lateral patterning processes. The vertical stacking approach simplifies the manufacturing workflow compared to continuing to shrink lateral feature sizes, thereby reducing manufacturing complexity.
3Ease of manufacture
If horizontal gate dielectric layer has uniform thickness, then manufacturing is simpler, but electrical leakage prevention is reduced at connection regions
Solution Approach 1:
The horizontal gate dielectric layer is designed with non-uniform thickness, where the thickness varies across different regions of the substrate. Specifically, the dielectric layer is thicker at the connection region compared to the cell array region. This local variation optimizes electrical isolation and prevents leakage at the connection region while maintaining manufacturability through controlled deposition processes.
Data Source
AI summary
A three-dimensional semiconductor memory device may include a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region. The memory device may include an electrode structure extending from the cell array region toward the connection region and comprising electrodes stacked on the substrate, a horizontal gate dielectric layer between the electrode structure and the substrate and including a first portion on the cell array region and a second portion on the connection region, the second portion thicker than the first portion in the vertical direction, first vertical channels on the cell array region and penetrating the electrode structure and the first portion of the horizontal gate dielectric layer, and second vertical channels on the connection region and penetrating the electrode structure and the second portion of the horizontal gate dielectric layer.