3D Semiconductor Memory Stack With Variable-Width Pad Layout
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Solution Overview
Problem
Current three-dimensional semiconductor memory devices face challenges in increasing memory capacity without significantly increasing manufacturing costs and reducing pad region area to enhance integration density.
Innovation Solution
A three-dimensional semiconductor device is designed with stacked structures and vertical channel structures, where conductive layers are arranged with specific dimensions and orientations, and pads are formed using photoresist films with varying widths to minimize pad region area and maximize memory capacity, allowing for efficient electrical connections and reduced chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase memory capacity, then the memory capacity increases, but the pad region area increases
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional stacked structure, where memory cells are arranged vertically across multiple layers. This dimensional change allows significant increase in memory capacity while maintaining a compact footprint, as the storage density is multiplied by the number of stacked layers rather than requiring proportional expansion of the pad region area.
Solution Approach 2:
The patent implements a stacked structure where multiple conductive layers and memory cell layers are nested vertically, with each layer containing memory cells that are spatially organized in a compact manner. The nested arrangement of conductive layers, insulating layers, and memory cell layers within a vertical stack enables high-density storage without proportionally increasing the horizontal pad region area.
2Quantity of substance
If three-dimensional stacked structures are formed to increase memory capacity, then the memory capacity increases, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the three-dimensional memory structure into repeating modular units, where each unit consists of a conductive layer, insulating layer, and memory cell layer stacked together. This segmentation into standardized modules simplifies manufacturing by allowing repeated deposition and patterning cycles using the same process parameters, reducing overall manufacturing complexity despite the increased memory capacity.
Solution Approach 2:
The patent forms the complete stacked structure of conductive layers and insulating layers before introducing the memory material into the pores. This preliminary formation of the structural framework simplifies subsequent processing steps, as the memory material can be directly deposited or infused into the pre-formed porous structure without requiring complex simultaneous multi-material deposition.
Data Source
AI summary
A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.