3D Memory Cell Pillar Structure With Variable Word Line Thickness
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Solution Overview
Problem
Conventional two-dimensional memory devices face limitations in integration density and cost due to the area occupied by unit memory cells, which are affected by the technique for forming fine patterns, and there is a need for manufacturing techniques that can reduce bit cost and ensure reliable production of three-dimensional semiconductor devices.
Innovation Solution
A semiconductor device with a stack of word lines and insulating patterns vertically stacked on a substrate, where memory cells are formed at the junctions of cell pillars and word lines, with varying thicknesses and diameters of word lines and cell pillars to optimize integration density and reliability, including nonvolatile memory cells with charge storage elements and data storage elements made of materials with variable resistance properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional two-dimensional memory devices are used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from conventional two-dimensional memory architecture to a three-dimensional stacked architecture. Multiple memory layers are vertically stacked with word lines and bit lines extending through multiple layers, enabling significantly higher integration density by utilizing the vertical dimension for memory cell arrangement.
Solution Approach 2:
The patent implements a nested structure where cell pillars are formed within recess regions that are defined by the stacked memory layers. The cell pillars extend vertically through multiple memory layers, with charge storage elements nested within the pillar structure, creating a compact nested arrangement that maximizes space utilization.
2Reliability
If uniform thickness word lines are used, then manufacturing is easier, but reliability is reduced
Solution Approach 1:
The patent implements word lines with non-uniform thickness where the thickness varies at different vertical positions and horizontal locations. Specifically, first word lines have different thicknesses than second word lines, and third word lines have different thicknesses again. This local variation in thickness is designed to compensate for process variations and ensure reliable memory cell operation across different regions of the device.
3Manufacturing precision
If fine pattern techniques are improved, then unit memory cell area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the memory device into multiple distinct layers including first memory layers, second memory layers, and third memory layers stacked vertically. Each layer contains specific components such as word lines, bit lines, and cell pillars. This segmentation allows for modular manufacturing where each layer can be formed and processed separately, reducing the overall manufacturing complexity despite the need for fine pattern techniques.
Data Source
AI summary
A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.