3D Memory Verification Mechanism for Threshold Voltage Stability
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Solution Overview
Problem
Flash memory devices face challenges in ensuring data reliability due to unintended changes in threshold voltage of memory cells during programming and verification processes, leading to potential errors and over-programming issues.
Innovation Solution
The implementation of a memory device with a verification mechanism that re-verifies the threshold voltage of memory cells after a certain period following the initial verify-pass, using multiple verify levels and slow programming techniques to adjust the charge injection, thereby preventing threshold voltage falls and maintaining data accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a first program voltage is applied to program memory cells and a first verify voltage is applied to verify programming completion, then programming progress can be monitored, but threshold voltage may unintentionally change during the process leading to data errors
Solution Approach 1:
The patent applies a second program voltage to memory cells that passed the first verification before applying the second verify voltage. This preliminary re-programming action prevents threshold voltage degradation and ensures data reliability by proactively addressing potential verification failures before they occur.
Solution Approach 2:
The patent uses verification results from the first verify operation to determine which memory cells require additional programming. The second program voltage is selectively applied based on feedback from the first verification, creating a closed-loop control system that maintains threshold voltage stability and prevents data errors.
2Reliability
If multiple verification steps are performed to ensure data accuracy, then data reliability improves, but programming time and process complexity increase
Solution Approach 1:
The patent applies the second program voltage selectively only to memory cells that passed the first verification, rather than re-programming all memory cells. This localized approach reduces unnecessary programming operations and minimizes additional programming time while maintaining high data reliability.
Solution Approach 2:
The patent performs a second verification on memory cells that already passed the first verification, applying slightly more verification than the minimum single check. This partial re-verification ensures data reliability without requiring complete re-programming of all cells, balancing time consumption with reliability improvement.
3Manufacturing precision
If charge injection is increased to ensure programming completion, then programming effectiveness improves, but threshold voltage distribution broadens leading to state overlap and errors
Solution Approach 1:
The patent applies programming voltage in periodic pulses with controlled width and amplitude rather than continuous high-voltage injection. The second program voltage is applied for a controlled duration after the first verification, preventing excessive charge injection that would broaden threshold voltage distribution while ensuring programming completion.
Solution Approach 2:
The patent changes programming parameters by applying a second program voltage with controlled characteristics (voltage level, pulse width) that are optimized to prevent threshold voltage broadening. The verification voltages are also adjusted to detect threshold voltage changes accurately, maintaining precise state separation while ensuring programming effectiveness.
Data Source
AI summary
According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.