3D Semiconductor Memory Verification Sequence Optimization
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Solution Overview
Problem
Current 3D semiconductor memory devices face challenges in increasing memory capacity while maintaining high-speed operation, particularly in verifying programming and erasure operations, as upper layers are more susceptible to errors due to larger channel diameters leading to reduced electric fields and potential erase failures.
Innovation Solution
The 3D semiconductor memory device employs a controller that applies verifying voltages in a reverse order of word lines, starting from the upper layer with the largest channel diameter, followed by the lower layer, to quickly detect and address potential errors in erasure operations, thereby accelerating the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased by vertically stacking cell transistors, then storage density is improved, but operation speed deteriorates due to longer verification time
Solution Approach 1:
The patent applies preliminary action by performing verification on upper-layer memory cells (which have higher failure probability due to larger channel diameters) before verifying lower-layer cells. This reordering of verification steps allows the system to quickly identify and handle potential failures in upper layers first, reducing the total verification time for multi-layer memory structures and thus improving operation speed while maintaining high memory capacity.
2Ease of manufacture
If channel diameter is increased in upper layers, then manufacturing ease is improved, but reliability deteriorates due to reduced electric field strength
Solution Approach 1:
The patent performs preliminary verification on upper-layer memory cells that have larger channel diameters and higher susceptibility to erase failures. By verifying these cells first before lower-layer cells, the system can detect and handle potential failures early in the verification process, compensating for the reduced reliability caused by larger channel diameters while maintaining manufacturing ease.
3Device complexity
If verification is performed sequentially from lower layer to upper layer, then process simplicity is maintained, but loss of time increases due to delayed detection of upper layer failures
Solution Approach 1:
The patent inverts the conventional verification sequence by verifying upper-layer memory cells first and then lower-layer cells, rather than proceeding from lower to upper layers. This inversion allows the system to detect failures in upper layers (which have higher failure probability) earlier in the process, reducing the average verification time while maintaining relatively simple process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances operation speed by prioritizing the verification of memory cells most likely to fail first, ensuring rapid detection of erase failures and improving overall memory device performance.
Implementation Method 1
upper layers are more susceptible to errors due to larger channel diameters leading to reduced electric fields and potential erase failures
Data Source
AI summary
A 3D semiconductor memory device including a plurality of memory cell strings, includes a substrate and a channel that extends from the substrate. Memory cells may be disposed in layers in which the diameter of the channel varies. A programming verification operation may be carried out in a sequence whereby memory cells more likely to fail in programming are verified before attempting to verify memory cells that are less likely to fail programming. In an exemplary embodiment, the verification operation is performed on a memory cell disposed in a layer associated with a larger-diameter channel before performing the verification on a memory cell disposed in a layer associated with a smaller-diameter channel. In an exemplary embodiment, if a verification process detects a programming failure, the verification of subsequent memory cells is cancelled.