3D Memory Device Vertical Bit Line Integration
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Solution Overview
Problem
The integration density of two-dimensional semiconductor devices is limited by the cost and complexity of fine pattern formation, necessitating the development of three-dimensional memory devices with improved packing efficiency.
Innovation Solution
A three-dimensional memory device design featuring vertically oriented bit and plate lines, a transistor with laterally oriented active regions and channel portions, and a capacitor positioned between the active region and plate line, allowing for increased integration density through advanced structural arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor device structure is used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional structure by vertically stacking bit lines, plate lines, transistors, and capacitors. The bit line and plate line extend in the first direction (vertical), while the active region extends in the second direction (lateral), creating a 3D configuration that increases integration density without significantly complicating the manufacturing process
2Quantity of substance
If three-dimensional memory device structure is used, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The active region is segmented into multiple cylinders arranged in the second direction, with channel portions positioned between adjacent cylinders. This segmentation allows for better spatial utilization and improved integration density while maintaining a structured, manufacturable design. The surrounding gate electrode is also segmented to wrap around each channel portion individually
Solution Approach 2:
The surrounding gate electrode is configured to surround and wrap around the channel portion, creating a nested structure where the gate electrode encloses the active region. This nesting approach maximizes the use of vertical space and improves integration density without requiring overly complex manufacturing steps
3Quantity of substance
If fine pattern formation technology is advanced to increase integration density, then manufacturing cost increases
Solution Approach 1:
By moving to a three-dimensional structure with vertical bit lines and plate lines, the patent achieves higher integration density without requiring extremely fine lateral pattern formation. The vertical stacking allows for denser packing while using relatively standard lithography and fabrication techniques, thereby avoiding the need for highly expensive advanced fine pattern formation equipment
Data Source
AI summary
A memory cell includes a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor provided with an active region that is laterally oriented in a second direction crossing the bit line and includes a first active cylinder, a second active cylinder, and at least one channel portion oriented laterally between the first active cylinder and the second active cylinder; a word line extending in a third direction while surrounding the at least one channel portion of the active region; and a capacitor oriented laterally in the second direction between the active region and the plate line.