3D Non-Volatile Memory Vertical Capacitor for Higher Capacitance
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Solution Overview
Problem
Current non-volatile memory devices face challenges in achieving high capacitance without increasing chip size, particularly in three-dimensional structures where space efficiency is crucial.
Innovation Solution
The implementation of a vertical capacitor structure using dummy common source lines and dummy contact plugs, which are electrically isolated and formed in regions outside the memory cell arrays, allowing for increased capacitance without expanding the chip size by utilizing existing fabrication processes for common source lines and input/output contact plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitor structures are used, then chip size remains small, but capacitance is insufficient
Solution Approach 1:
The patent transitions from planar capacitor structures to vertical three-dimensional capacitor structures. The dummy common source lines extend in the third direction (vertical direction) perpendicular to the chip surface, and dummy contact plugs connect vertically to these lines, creating vertical capacitors that utilize the vertical dimension to increase capacitance without expanding chip area.
Solution Approach 2:
The patent reuses existing dummy common source lines and dummy contact plugs (originally intended as placeholder structures) to serve dual purposes: maintaining structural integrity during fabrication and functioning as capacitor electrodes. This multi-functional use of existing structures increases capacitance without requiring additional dedicated capacitor components.
2Productivity
If three-dimensional structure is implemented, then integration density increases, but space efficiency becomes challenging
Solution Approach 1:
The dummy common source lines and dummy contact plugs serve multiple functions: they maintain structural integrity during fabrication processes, provide electrical isolation, and function as capacitor electrodes. This multi-functionality allows the three-dimensional structure to achieve high integration density without sacrificing space efficiency, as the same structures fulfill multiple roles.
Solution Approach 2:
By extending dummy common source lines in the vertical third direction and creating vertical capacitor structures, the patent utilizes the vertical dimension to increase integration density. This approach maintains space efficiency by stacking functions vertically rather than expanding horizontally, allowing higher integration without compromising space utilization.
Data Source
AI summary
The present disclosure relates to a semiconductor device, and more particularly, relates to a non-volatile memory device having a three-dimensional structure. The non-volatile memory device according to an embodiment of the present disclosure includes a first chip having a peripheral circuit therein and a second chip that is stacked on the first chip and that includes memory blocks. The second chip includes a common source line that has a plate shape and extends in first and second directions, first and second dummy common source lines disposed at a same height level as the common source line, an upper insulating layer that covers the common source line and the first and second dummy common source lines, and first and second dummy contact plugs extending in a third direction and that are electrically connected to the first and second dummy common source lines, respectively, and used as electrodes of a vertical capacitor.