3D Non-Volatile Memory Vertical Channel Integration Density
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Solution Overview
Problem
2-dimensional semiconductor memory devices face challenges with increasing integration density, leading to interference and disturbance between adjacent devices, which complicates multi-level cell operations and limits data storage capacity.
Innovation Solution
A 3-dimensional non-volatile memory device is developed with vertical channel layers, alternately stacked interlayer and conductive layers, a charge trap layer with varying thickness, and a blocking insulating layer to improve integration density and reliability, featuring a manufacturing method that includes forming channel holes, charge trap, and conductive layers with specific etching and oxidation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2-dimensional memory device integration density is increased, then data storage capacity improves, but interference and disturbance between adjacent devices increases
Solution Approach 1:
The patent transitions from 2-dimensional planar memory cell arrangement to 3-dimensional vertical stacking architecture. Memory cells are stacked in the vertical direction perpendicular to the substrate, allowing multiple layers of memory cells to be formed. This dimensional change increases storage capacity without increasing lateral footprint and reduces interference between adjacent cells by separating them in the vertical dimension.
Solution Approach 2:
The memory device is divided into multiple stacked layers including alternate conductive layers and interlayer insulating layers. Each layer is segmented into discrete memory cells with isolated charge trap regions. This segmentation allows independent operation of each cell, reducing cross-talk and interference between adjacent cells while maintaining high integration density.
2Reliability
If charge trap layer thickness is reduced in first regions, then back tunneling of charges is reduced, but data storage capacity in those regions decreases
Solution Approach 1:
The charge trap layer is designed with non-uniform thickness: thinner in first regions between conductive layers and vertical channel layers to reduce back tunneling and improve retention, and thicker in second regions between interlayer insulating layers and vertical channel layers to maintain data storage capacity. This local variation in thickness allows simultaneous optimization of both reliability and storage capacity in different regions of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances integration density and reliability by reducing back tunneling of charges, thereby improving retention characteristics and data storage capacity while minimizing interference between memory cells.
Implementation Method 1
reducing back tunneling of charges
Implementation Method 2
forming blocking insulating layers by oxidizing portions of the charge trap layers
Data Source
AI summary
A 3-dimensional non-volatile memory device, a memory system including the same, and a method of manufacturing the same comprise vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of conductive layers alternately formed along the vertical channel layers, a charge trap layer surrounding the vertical channel layers, the charge trap layer having a smaller thickness in a plurality of first regions, interposed between the plurality of conductive layers and the vertical channel layers, than in a plurality of second regions, interposed between the plurality of interlayer insulating layers and the vertical channel layers and a blocking insulating layer formed in each of the plurality of first regions, between the plurality of conductive layers and the charge trap layer.