3D Memory Vertical Channels Shared Bitlines
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Solution Overview
Problem
Three-dimensional (3D) memory devices face challenges in increasing storage capacity and integration density without increasing channel resistance, which affects current flow and sensing capabilities.
Innovation Solution
The design includes a 3D memory device with multiple vertical channel structures, shared bit lines and common source lines, and strategically positioned string selection transistors with different threshold voltages to optimize channel length and reduce resistance, allowing for increased storage capacity and integration density without compromising current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel length is increased to increase storage capacity and integration density, then the storage capacity and integration density are improved, but the channel resistance increases which affects current flow and sensing capabilities
Solution Approach 1:
The patent transitions from planar memory architecture to three-dimensional vertical channel structures. Multiple memory blocks are stacked vertically with bit lines extending horizontally between them, allowing storage capacity to increase in the vertical dimension while maintaining horizontal current flow paths that avoid excessive resistance accumulation.
Solution Approach 2:
The memory device is divided into multiple discrete memory blocks (first memory block, second memory block, third memory block) that can be independently addressed and accessed. Each block contains separate vertical channel structures, allowing the system to achieve high total storage capacity while maintaining manageable channel resistance within each individual block through shared bit lines.
2Quantity of substance
If multiple memory blocks are added to increase storage capacity, then the integration density is improved, but the number of bit lines and common source lines increases leading to higher process costs
Solution Approach 1:
Bit lines are designed to serve multiple functions by being shared across multiple memory blocks. A single bit line extends horizontally and provides data access to multiple vertically-stacked memory blocks, eliminating the need for separate bit lines for each block and thereby reducing manufacturing complexity and cost.
Solution Approach 2:
Multiple memory blocks share common bit lines and common source lines. The first and second memory blocks share a first bit line, while the second and third memory blocks share a first common source line. This merging of resources reduces the total number of conductive structures required, lowering process costs while maintaining high integration density.
Data Source
AI summary
A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other.