3D Memory Device With Vertical Gate Electrodes
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Solution Overview
Problem
Current three-dimensional NAND memory devices face challenges in achieving simpler electrical connections and tighter threshold voltage distribution, which limits memory speed and efficiency.
Innovation Solution
The development of a three-dimensional memory device with an alternating stack of source and drain layers over a substrate, featuring vertically extending gate electrodes and semiconductor channels that surround memory films, allowing for improved electrical connections and increased channel width for faster memory speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional three-dimensional NAND memory device structure is used, then manufacturing process is established, but electrical connections are complex and memory speed is limited
Solution Approach 1:
The patent inverts the conventional structure by making gate electrodes vertical rather than horizontal, and by alternating source and drain layers horizontally rather than having them at opposite ends of vertical channels. This structural inversion simplifies electrical connections and enables faster memory operation.
Solution Approach 2:
The patent transitions from a conventional horizontal gate electrode arrangement to vertical gate electrodes, utilizing the vertical dimension for gate control while maintaining horizontal source-drain alternation. This dimensional reorganization simplifies the electrical connection architecture.
2Manufacturing precision
If conventional memory device structure is used, then basic functionality is achieved, but threshold voltage distribution is loose
Solution Approach 1:
The patent implements local quality by providing individual gate electrode control over each semiconductor channel region. This localized control enables precise threshold voltage adjustment for each channel, resulting in tighter overall threshold voltage distribution and improved memory efficiency.
3Speed
If conventional structure is used, then device is functional, but channel width is limited affecting memory speed
Solution Approach 1:
The patent segments the memory structure into alternating source and drain layers with vertical gate electrodes controlling semiconductor channels between them. This segmentation enables increased effective channel width while maintaining functional integrity, thereby improving memory speed.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, gate electrodes vertically extending through each of the source layers and the drain layers of the alternating stack, memory films laterally surrounding a respective one of the gate electrodes, and semiconductor channels laterally surrounding a respective one of the memory films and connected to a respective vertically neighboring pair of a source layer and a drain layer. An array of memory openings can vertically extend through the alternating stack, and each of the gate electrodes can be located within a respective one of the memory openings.