3D Semiconductor Memory Vertical Pad Structure
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in integration due to the high cost of advanced pattern forming technologies, necessitating the development of three-dimensional semiconductor memory devices with improved electrical characteristics.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a vertical structure comprising a vertical channel portion, a charge storing structure, and a pad configuration that includes a first pad portion within the internal space of the vertical structure and a second pad portion extending onto the top surface of the charge storing structure, with the first pad portion being horizontally overlapped with the erase gate electrode to enhance electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor memory devices are used, then manufacturing process is simpler, but integration is limited due to area constraints and high cost of fine pattern forming technology
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked in the vertical direction, allowing integration scaling without requiring finer lateral patterning. This dimensional change enables higher integration while avoiding the need for expensive advanced lithography equipment.
Solution Approach 2:
The patent implements a vertically stacked architecture where multiple memory cells are nested one above another in the vertical direction. Each memory cell layer contains charge storing structures and channel portions that are stacked sequentially, creating a nested three-dimensional configuration that increases storage density within the same footprint area.
2Productivity
If three-dimensional vertically stacked memory cells are implemented, then integration is improved, but device thickness increases
Solution Approach 1:
The patent divides the three-dimensional memory structure into multiple discrete memory cell layers stacked vertically. Each layer contains separated components including charge storing structures, channel portions, and gate electrodes. This segmentation allows for modular stacking that increases integration while managing device thickness through layered architecture.
Solution Approach 2:
The patent employs selective doping with different conductivity types in different regions of the vertical structure. First pad portions have first conductivity type doping while second pad portions have second conductivity type doping. This local quality variation optimizes electrical characteristics in different regions, enabling improved erase operation properties while maintaining the vertical stacked architecture.
3Ease of manufacture
If standard pad configuration is used in vertical structure, then manufacturing is simpler, but electrical characteristics particularly erase operation property deteriorates
Solution Approach 1:
The patent implements a dual-region pad structure where first pad portions and second pad portions are differently doped with opposite conductivity types. The first pad portions extend into internal spaces and are horizontally overlapped with erase gate electrodes, while second pad portions are positioned on top surfaces. This local quality differentiation optimizes electrical fields for erase operations while maintaining manufacturability.
Solution Approach 2:
The first pad portions act as intermediary structures that extend into internal spaces of the vertical memory cells and are horizontally overlapped with erase gate electrodes. This intermediary configuration creates optimized electrical pathways that enhance erase operation properties by facilitating better charge removal from the charge storing structures during erase cycles.
Data Source
AI summary
A three-dimensional semiconductor memory device may include a stack including gate electrodes sequentially stacked on a substrate and a vertical structure penetrating the stack. The vertical structure may include a vertical channel portion, a charge storing structure on an outer side surface of the vertical channel portion, and a pad. The pad may include a first pad portion disposed in an internal space surrounded by the vertical channel portion and a second pad portion provided on the first pad portion and extended onto a top surface of the charge storing structure. A portion of the first pad portion may be disposed at the same level as an uppermost electrode of the gate electrodes.