3D Non-Volatile Memory Layout With Vertical Passive Elements
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing three-dimensional non-volatile memory devices face challenges in increasing capacity while minimizing chip size, particularly due to the need for high-capacity passive elements in peripheral circuits.
Innovation Solution
A non-volatile memory device with a chip-to-chip structure, where a second chip is stacked on a first chip, incorporating dummy pads and contact plugs to form vertical capacitors and resistors, which are integrated into the peripheral circuit region without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked on the substrate is increased to increase memory capacity, then the storage capacity is improved, but the chip size increases due to the need for high-capacity passive elements in peripheral circuits
Solution Approach 1:
The patent transitions from planar passive elements to vertically stacked passive elements (capacitors and resistors) in the third dimension. Multiple passive elements are stacked above each other in the vertical direction, allowing high-capacity passive elements to be formed without increasing the horizontal chip area, thus resolving the contradiction between memory capacity and chip size
Solution Approach 2:
The patent implements a nested structure where passive elements (capacitors and resistors) are stacked within each other in the vertical direction. The lower passive element is positioned beneath the upper passive element, creating a space-efficient nested arrangement that maximizes passive element capacity within the limited chip footprint
Data Source
AI summary
A non-volatile memory device includes a first chip including a first substrate and a circuit element, and a second chip stacked on the first chip. The second chip includes a second substrate including a first cell region and a second cell region, gate electrodes stacked on the second cell region of the second substrate, wherein the gate electrodes are between the second substrate and the first chip, an upper insulating layer configured to cover the second substrate, dummy pads and input/output pads on the upper insulating layer, a cover layer on the upper insulating layer to cover the dummy pads, wherein the cover layer is configured to expose the input/output pads to an outside, and dummy contact plugs on one side of the second substrate, wherein the dummy contact plugs are configured to penetrate the upper insulating layer and electrically connect the dummy pads and the circuit element.